參數(shù)資料
型號: XR19L200IL32-0A-EB
廠商: Exar Corporation
文件頁數(shù): 15/40頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR XR19L200 32QFN
標準包裝: 1
系列: *
XR19L200
22
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced LOW).
This condition remains, until disabled by setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) LOW for alerting the remote receiver of a line break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
4.8
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# output is not available as an output on this device. But for 16C550 compatibility, it can still be used
in internal loopback mode.
Logic 0 = Force DTR output HIGH (default).
Logic 1 = Force DTR output LOW.
TABLE 9: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
0
No parity
0
1
Odd parity
0
1
Even parity
1
0
1
Force parity to mark,
“1”
1
Forced parity to
space, “0”
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