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參數(shù)資料
| 型號： | XR19L200IL32-0A-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 13/40頁 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR19L200 32QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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XR19L200
20
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 7).
ISR[4]: Xoff/Xon or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s). If this is an Xoff/Xon interrupt, it can be cleared by a read to the ISR. If it is a special
character interrupt, it can be cleared by reading ISR or it will automatically clear after the next character is
received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has been de-
asserted.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.6
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select (Legacy)
This bit has no function and should be left at ’0’.
FCR[5:4]: Transmit FIFO Trigger Select
(’00’ = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 8 below shows the selections. EFR bit-4 must
be set to ‘1’ before these bits can be accessed.
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參數(shù)描述 |
|---|---|
| XR19L200IL32-0B-EB | 功能描述:界面開發(fā)工具 Supports L200 32 pin QFN, PCI Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR19L200IL32-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR19L202 | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
| XR19L202IL48 | 制造商:EXAR 制造商全稱:EXAR 功能描述:TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER |
| XR19L202IL48-0B-EB | 功能描述:界面開發(fā)工具 Supports L202 48 pin QFN,PCI Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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