- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16523 > XR16V2752IL-0B-EB (Exar Corporation)EVAL BOARD FOR V2752 32QFN PDF資料下載
參數(shù)資料
| 型號(hào)： | XR16V2752IL-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 4/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR V2752 32QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁
XR16V2752
12
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.0.2
2.11
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X internal
clock. A bit time is 16 (8) clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the
number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and
TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
2.11.1
Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.11.2
Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
2.11.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X or 8X
Clock
(EMSR Bit-7)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EEU-FR1J271L | CAP ALUM 270UF 63V 20% RADIAL |
| UPA0J561MPD1TD | CAP ALUM 560UF 6.3V 20% RADIAL |
| H3AKH-3036G | IDC CABLE - HSC30H/AE30G/HPK30H |
| EBM28DTAD-S189 | CONN EDGECARD 56POS R/A .156 SLD |
| MCP1318T-46LE/OT | IC SUPERVISOR 4.6V PP/PP SOT23-5 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16V2752IL32 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
| XR16V2752IL-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16V2752ILTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 64Byte FIFO 2.5V/3.3V 32-Pin QFN EP T/R 制造商:Exar Corporation 功能描述:XR16V2752ILTR-F |
| XR16V554 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO |
| XR16V554_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。