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參數資料
型號: XR16V2752IL-0B-EB
廠商: Exar Corporation
文件頁數: 36/51頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR V2752 32QFN
標準包裝: 1
系列: *
XR16V2752
41
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
AC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=-40
O TO +85OC, VCC=2.25 - 3.63V, 70 PF LOAD WHERE APPLICABLE
SYMBOL
PARAMETER
LIMITS
2.5V ± 10%
MIN
MAX
LIMITS
3.3V ± 10%
MIN
MAX
UNIT
XTAL1
UART Crystal Oscillator
24
MHz
ECLK
External Clock
50
64
MHz
TECLK
External Clock Time Period
10
7
ns
TAS
Address Setup Time
0
ns
TAH
Address Hold Time
0
ns
TCS
Chip Select Width
50
40
ns
TRD
IOR# Strobe Width
50
40
ns
TDY
Read Cycle Delay
50
40
ns
TRDV
Data Access Time
45
35
ns
TDD
Data Disable Time
25
ns
TWR
IOW# Strobe Width
50
40
ns
TDY
Write Cycle Delay
50
40
ns
TDS
Data Setup Time
10
ns
TDH
Data Hold Time
5
ns
TWDO
Delay From IOW# To Output
50
ns
TMOD
Delay To Set Interrupt From MODEM Input
50
ns
TRSI
Delay To Reset Interrupt From IOR#
50
ns
TSSI
Delay From Stop To Set Interrupt
1
Bclk
TRRI
Delay From IOR# To Reset Interrupt
45
ns
TSI
Delay From Stop To Interrupt
45
ns
TINT
Delay From Initial INT Reset To Transmit Start
8
24
8
24
Bclk
TWRI
Delay From IOW# To Reset Interrupt
45
ns
TSSR
Delay From Stop To Set RXRDY#
1
Bclk
TRR
Delay From IOR# To Reset RXRDY#
45
ns
TWT
Delay From IOW# To Set TXRDY#
45
ns
TSRT
Delay From Center of Start To Reset TXRDY#
8
Bclk
TRST
Reset Pulse Width
40
ns
Bclk
Baud Clock
16X or 8X of data rate
Hz
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