REV. 1.0.2 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE 2.11 Receiver The receiver section contain" />
參數(shù)資料
型號(hào)： XR16V2651IM-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 7/51頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR V2651 48TQFP
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16V2651
15
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
2.11
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 32 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X/4X clock (DLD[5:4]) for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the 16X/8X/4X clock rate. After 8 clocks
(or 4 if 8X or 2 if 4X) the start bit period should be at the center of the start bit. At this time the start bit is
sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same
manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon
unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are
immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data
ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data
delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4
word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR
interrupt is enabled by IER bit-0. See Figure 8 and Figure 9 below.
2.11.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 32 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
R egister (R SR )
Receive
D ata Byte
and Errors
R H R Interrupt (ISR bit-2)
Receive Data
H olding R egister
(R H R)
RXFIFO 1
16X or 8X or 4X C lock
( D LD[5:4] )
R eceive D ata C haracters
D ata Bit
Validation
Error
Tags in
LS R bits
4:2
相關(guān)PDF資料
PDF描述
VE-JVN-EZ-S CONVERTER MOD DC/DC 18.5V 25W
EEM28DTMN-S189 CONN EDGECARD 56POS R/A .156 SLD
GSM11DRTH-S13 CONN EDGECARD 22POS .156 EXTEND
A3DDH-1636G IDC CABLE - AKR16H/AE16G/AKR16H
VE-JVK-EZ-S CONVERTER MOD DC/DC 40V 25W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16V2651IM-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16V2651IMTR-F 制造商:Exar Corporation 功能描述:UART 2-CH 32Byte FIFO 2.5V/3.3V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16V2651IMTR-F
XR16V2652 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
XR16V2652_07 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
XR16V2652IJ 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*