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參數(shù)資料
| 型號(hào)： | XR16V2651IM-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 49/51頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR V2651 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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XR16V2651
7
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO AND POWERSAVE FEATURE
1.0 PRODUCT DESCRIPTION
The XR16V2651 (V2651) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver
and Transmitter (UART). Its features set is compatible to the XR16V2550 and XR16V2650 devices but offers
Intel or Motorola data bus interface and PowerSave to isolate the data bus interface during Sleep mode.
Hence, the V2651 adds 3 more inputs: 16/68#, PwrSave and CLKSEL pins. Each UART is independently
controlled having its own set of device configuration registers. The configuration registers set is 16550 UART
compatible for control, status and data transfer. Additionally, each UART channel has 32-bytes of transmit and
receive FIFOs, automatic RTS/CTS hardware flow control with hysteresis control, automatic Xon/Xoff and
special character software flow control, selectable transmit and receive FIFO trigger levels, infrared encoder
and decoder (IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of divide by 1 or 4.
The XR16V2651 can operate from 2.25V to 3.6V with 5 volt tolerant inputs. The V2651 is fabricated with an
advanced CMOS process.
Enhanced Features
The V2651 DUART provides a solution that supports 32 bytes of transmit and receive FIFO memory, instead of
16 bytes in the ST16C2550 or one byte in the ST16C2450. The V2651 is designed to work with low supply
voltage and high performance data communication systems, that require fast data processing time. Increased
performance is realized in the V2651 by the larger transmit and receive FIFOs, FIFO trigger level control, and
automatic flow control mechanism. This allows the external processor to handle more networking tasks within
a given time. For example, the ST16C2550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms
(This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This means the
external CPU will have to service the receive FIFO at 1.53 ms intervals. However with the 32 byte FIFO in the
V2651, the data buffer will not require unloading/loading for 3.06 ms. This increases the service interval giving
the external CPU additional time for other applications and reducing the overall UART interrupt servicing time.
In addition, the selectable FIFO trigger level interrupt and automatic hardware/software flow control is uniquely
provided for maximum data throughput performance especially when operating in a multi-channel system. The
combination of the above greatly reduces the CPU’s bandwidth requirement, increases performance, and
reduces power consumption.
Data Bus Interface, Intel or Motorola Type
The V2651 provides a single host interface for the 2 UARTs and supports Intel or Motorola microprocessor
(CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type
of CPUs using IOR#, IOW# and CSA# or CSB# inputs for data bus operation. The Motorola bus compatible
interface instead uses the R/W#, CS# and A3 signals for data bus transactions. Few data bus interface signals
change their functions depending on user’s selection, see pin description for details. The Intel and Motorola
bus interface selection is made through the 16/68# pin.
Data Rate
The V2651 is capable of operation up to 4 Mbps at 3.3V with 16X internal sampling clock rate, 8 Mbps at 3.3V
with 8X sampling clock rate and 16 Mbps at 3.3V with 4X sampling clock rate. The device can operate with an
external 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of up to 64 MHz on XTAL1 pin.
With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit for data
rates of up to 3.68 Mbps.
The rich feature set of the V2651 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, programmable TX and RX baud rates, infrared
encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.
Following a power on reset or an external reset, the V2651 is software compatible with previous generation of
UARTs, 16C450, 16C550 and 16C650A.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16V2651IM-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16V2651IMTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 32Byte FIFO 2.5V/3.3V 48-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR16V2651IMTR-F |
| XR16V2652 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO |
| XR16V2652_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO |
| XR16V2652IJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
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