參數(shù)資料
型號: XR16M2752IJ-0B-EB
廠商: Exar Corporation
文件頁數(shù): 29/51頁
文件大?。?/td> 0K
描述: EVAL BOARD FOR M2752-B 44PLCC
標(biāo)準包裝: 1
系列: *
XR16M2752
35
REV. 1.0.0
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is
intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are
initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When
this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user
should ensure that LCR Bit-7 of both channels are in the same state before executing a concurrent write to the
registers at address 0, 1, or 2.
Logic 0 = No concurrent write (default).
Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
AFR[2:1]: MF# Output Select
These bits select a signal function for output on the MF# A/B pins. These signal function are described as:
OP2#, BAUDOUT#, or RXRDY#. Only one signal function can be selected at a time.
AFR[7:3]: Reserved
All are initialized to logic 0.
4.14
Device Identification Register (DVID) - Read Only
This register contains the device ID (0x0A for XR16M2752). Prior to reading this register, DLL and DLM should
be set to 0x00 (DLD = 0xXX).
4.15
Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00 (DLD = 0xXX).
4.16
Trigger Level Register (TRG) - Write-Only
User Programmable Transmit/Receive Trigger Level Register. If both the TX and RX trigger levels are used,
the TX trigger levels must be set before the RX trigger levels.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
4.17
RX/TX FIFO Level Count Register (FC) - Read-Only
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count
Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is
suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter
FIFO (FCTR[7] = 1) can be read via this register. Reading this register is not recommended when transmitting
or receiving data.
4.18
Feature Control Register (FCTR) - Read/Write
This register controls the XR16M2752 new functions that are not available in ST16C2450 or ST16C2550.
BIT-2
BIT-1
MF# FUNCTION
0
OP2# (default)
0
1
BAUDOUT#
1
0
RXRDY#
1
Reserved
相關(guān)PDF資料
PDF描述
AQ1055N1S-T INDUCTOR 5.1NH 460MA 0402 SMD
VE-J0F-EZ-S CONVERTER MOD DC/DC 72V 25W
1-5504970-2 CA 62.5/125UMLDS SC TO SC
H8MMH-4036M DIP CABLE - HDM40H/AE40M/HDM40H
VE-JTF-EZ-S CONVERTER MOD DC/DC 72V 25W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16M2752IJ44 制造商:EXAR 制造商全稱:EXAR 功能描述:1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
XR16M2752IJ44-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16M2752IL-0A-EB 功能描述:界面開發(fā)工具 Eval Board for XR16M2752IL-0A RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XR16M2752IL-0B-EB 功能描述:界面開發(fā)工具 Eval Board for XR16M2752IL Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
XR16M2752IL32 制造商:EXAR 制造商全稱:EXAR 功能描述:1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO