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參數(shù)資料
| 型號： | XR16L2752CJTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 46/49頁 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 64B DUAL 44PLCC |
| 標準包裝： | 500 |
| 特點： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
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XR16L2752
xr
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
6
1.0 PRODUCT DESCRIPTION
The XR16L2752 (2752) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware
flow control with hysteresis control, automatic Xon/Xoff and special character software flow control,
programmable transmit and receive FIFO trigger levels, FIFO level counters, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 6.25
Mbps with 8X sampling clock rate or 3.125 Mbps in the 16X rate. The XR16L2752 is a 2.25 to 5.5V device with
5 volt tolerant inputs. The 2752 is fabricated with an advanced CMOS process.
Enhanced Features
The 2752 DUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
128 bytes provided in the XR16C2852 and 16 bytes in the ST16C2552. The 2752 is designed to work with low
supply voltage and high performance data communication systems, that require fast data processing time.
Increased performance is realized in the 2752 by the larger transmit and receive FIFOs, FIFO trigger level
control, FIFO level counters and automatic flow control mechanism. This allows the external processor to
handle more networking tasks within a given time. For example, the ST16C2552 with a 16 byte FIFO, unloads
16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at
115.2 Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However
with the 64 byte FIFO in the 2752, the data buffer will not require unloading/loading for 6.1 ms. This increases
the service interval giving the external CPU additional time for other applications and reducing the overall
UART interrupt servicing time. In addition, the programmable FIFO level trigger interrupt and automatic
hardware/software flow control is uniquely provided for maximum data throughput performance especially
when operating in a multi-channel system. The combination of the above greatly reduces the CPU’s bandwidth
requirement, increases performance, and reduces power consumption.
The 2752 supports a half-duplex output direction control signaling pin, RTS# A/B, to enable and disable the
external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive
state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic
state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The
auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has
to set FCTR Bit-3 to “1”. This pin is normally high for receive state, low for transmit state.
Data Rate
The 2752 is capable of operation up to 3.125 Mbps at 5V with 16X internal sampling clock rate, and 6.25 Mbps
at 5V with 8X sampling clock rate. The device can operate with an external 24 MHz crystal on pins XTAL1 and
XTAL2, or external clock source of up to 50 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and
through a software option, the user can set the prescaler bit for data rates of up to 1.84 Mbps.
The rich feature set of the 2752 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable TX and RX baud rates, infrared
encoder/decoder interface, modem interface controls, and a sleep mode are all standard features.
Following a power on reset or an external reset, the 2752 is software compatible with previous generation of
UARTs 16C2552 and 16C2852.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16L2752IJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| XR16L2752IJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L2752IJTR-F | 制造商:Exar Corporation 功能描述:XR16L2752 Series 6.25 Mbps 5.5 V Dual UART With 64-Byte FIFO - PLCC-44 |
| XR16L570 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
| XR16L570_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
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