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參數(shù)資料
| 型號： | XR16L2752CJTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 23/49頁 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 64B DUAL 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
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xr
XR16L2752
REV. 1.2.1
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
3
PIN DESCRIPTIONS
Pin Description
NAME
44-PLCC
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
15
14
10
I
Address data lines [2:0]. These 3 address lines select one of the internal registers in
UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
I/O
Data bus lines [7:0] (bidirectional).
IOR#
24
I
Input/Output Read Strobe (active low). The falling edge instigates an internal read
cycle and retrieves the data byte from an internal register pointed to by the address
lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to
read it on the rising edge.
IOW#
20
I
Input/Output Write Strobe (active low). The falling edge instigates an internal write
cycle and the rising edge transfers the data byte on the data bus to an internal regis-
ter pointed by the address lines.
CS#
18
I
UART chip select (active low). This function selects channel A or B in accordance
with the logical state of the CHSEL pin. This allows data to be transferred between the
user CPU and the 2752.
CHSEL
16
I
Channel Select - UART channel A or B is selected by the logical state of this pin when
the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a
logic 1 selects UART channel A. Normally, CHSEL could just be an address line from
the user CPU such as A4. Bit-0 of the Alternate Function Register (AFR) can tempo-
rarily override CHSEL function, allowing the user to write to both channel register
simultaneously with one write cycle when CS# is low. It is especially useful during the
initialization routine.
INTA
34
O
UART channel A Interrupt output (active high). A logic high indicates channel A is
requesting for service. For more details, see
INTB
17
O
UART channel B Interrupt output (active high). A logic high indicates channel B is
requesting for service. For more details, see
TXRDYA#
1
O
UART channel A Transmitter Ready (active low). The output provides the TX
FIFO/THR status for transmit channel A. See Table 2.
TXRDYB#
32
O
UART channel B Transmitter Ready (active low). The output provides the TX FIFO/
THR status for transmit channel B.
See Table 2.
MODEM OR SERIAL I/O INTERFACE
TXA
38
O
UART channel A Transmit Data or infrared encoder data. Standard transmit and
receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be
HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is
enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XR16L2752IJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| XR16L2752IJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L2752IJTR-F | 制造商:Exar Corporation 功能描述:XR16L2752 Series 6.25 Mbps 5.5 V Dual UART With 64-Byte FIFO - PLCC-44 |
| XR16L570 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
| XR16L570_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
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