- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3761 > XR16L2752CJTR-F (Exar Corporation)IC UART FIFO 64B DUAL 44PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | XR16L2752CJTR-F |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 21/49頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC UART FIFO 64B DUAL 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)
XR16L2752
xr
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.2.1
28
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 11 for parity selection summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
BIT-2
WORD
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
TABLE 11: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
X
0
No parity
0
1
Odd parity
0
1
Even parity
1
0
1
Force parity to mark,
“1”
1
Forced parity to
space, “0”
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST16C650AIQ48TR-F | IC UART FIFO 32B 48TQFP |
| ST16C552ACJ68TR-F | IC UART FIFO 16B DUAL 68PLCC |
| ST16C650ACJ44TR-F | IC UART FIFO 32B 44PLCC |
| XR16V2552IL-F | IC UART FIFO 16B DUAL 32QFN |
| XR16L2552IM-F | IC UART FIFO 16B DUAL 48TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR16L2752IJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO |
| XR16L2752IJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L2752IJTR-F | 制造商:Exar Corporation 功能描述:XR16L2752 Series 6.25 Mbps 5.5 V Dual UART With 64-Byte FIFO - PLCC-44 |
| XR16L570 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
| XR16L570_07 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。