參數(shù)資料
型號: XR16L2750
廠商: Exar Corporation
英文描述: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
中文描述: 2.25V至5.5V的杜阿爾特64字節(jié)FIFO
文件頁數(shù): 33/49頁
文件大?。?/td> 602K
代理商: XR16L2750
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
á
33
4.15
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.16
Trigger Level Register (TRG) - Write-Only
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
4.17
RX/TX FIFO Level Count Register (FC) - Read-Only
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count
Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is
suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.
See
Table 12
.
FC[7:0]: RX/TX FIFO Level Count
Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter FIFO
(FCTR[7] = 1) can be read via this register.
4.18
Feature Control Register (FCTR) - Read/Write
This register controls the XR16L2750 new functions that are not available in ST16C2450 or ST16C2550.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See
Table 13
for more details.
FCTR[2]: IrDa RX Inversion
Logic 0 = Select RX input as encoded IrDa data (Idle state will be logic 0).
Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be logic 1).
FCTR[3]: Auto RS-485 Direction Control
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from low to high one bit time after the last stop bit of the last character is shifted out. Also,
the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The RTS#
output pin will automatically return to a logic low when a data byte is loaded into the TX FIFO. However,
RTS# behavior can be inverted by setting EMSR[3] = 1.
FCTR[5:4]: Transmit/Receive Trigger Table Select
See
Table 10
for more details.
Device Revision Register (DREV) - Read Only
T
ABLE
14: T
RIGGER
T
ABLE
S
ELECT
FCTR
B
IT
-5
FCTR
B
IT
-4
T
ABLE
0
0
Table-A (TX/RX)
0
1
Table-B (TX/RX)
1
0
Table-C (TX/RX)
1
1
Table-D (TX/RX)
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