參數(shù)資料
型號: XR16L2750
廠商: Exar Corporation
英文描述: 2.25V TO 5.5V DUART WITH 64-BYTE FIFO
中文描述: 2.25V至5.5V的杜阿爾特64字節(jié)FIFO
文件頁數(shù): 26/49頁
文件大?。?/td> 602K
代理商: XR16L2750
á
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
REV. 1.0.0
26
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive
FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the
trigger level.
Table 10
shows the complete selections. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
T
ABLE
10: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
FCTR
B
IT
-5
FCTR
B
IT
-4
FCR
B
IT
-7
FCR
B
IT
-6
FCR
B
IT
-5
FCR
BIT
-4
R
ECEIVE
T
RIGGER
L
EVEL
T
RANSMIT
T
RIGGER
L
EVEL
C
OMPATIBILITY
0
0
0
0
1
1
0
1
0
1
0
0
1 (default)
4
8
14
1 (default)
Table-A. 16C550, 16C2550,
16C2552, 16C554, 16C580
compatible.
0
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
24
28
16
8
24
30
Table-B. 16C650A compatible.
1
0
0
0
1
1
X
0
1
0
1
X
0
0
1
1
0
1
0
1
8
16
56
60
8
16
32
56
Table-C. 16C654 compatible.
1
1
X
X
Programmable
via TRG
register.
FCTR[7] = 0.
Programmable
via TRG
register.
FCTR[7] = 1.
Table-D. 16C850, 16L2752,
16C2850, 16C2852, 16C854,
16C864, 16C872 compatible.
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