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參數(shù)資料
| 型號： | XR-T7288 |
| 廠商： | Exar Corporation |
| 英文描述： | CEPT1 Line Interface |
| 中文描述： | CEPT1線路接口 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 293K |
| 代理商： | XR-T7288 |
XR-T7288
3
Rev. 1.01
PIN CONFIGURATION
28 Lead SOJ (Jedec, 0.300”)
T1
R1
SD
GNDA
V
DD
A
ZS
T2
V
DD
D
R2
GNDD
NC
FLM
SR/DR
BClk
LOS
LOC
HDB3/TNDATA
VIO/RNDATA
RClk
RDATA/RPDATA
TClk
TDATA/TPDATA
LP1
LP2
LP3
ALMT
RBC
TBC
28 Lead PDIP (0.300”)
13
16
14
15
1
2
3
4
5
6
7
8
9
10
28
27
26
25
24
23
22
21
20
19
11
18
12
17
28
1
15
14
2
3
4
5
6
7
17
16
8
9
19
18
10
11
23
22
21
20
27
26
25
24
12
13
T1
R1
SD
GNDA
V
DD
A
ZS
T2
V
DD
D
R2
GNDD
NC
FLM
SR/DR
BClk
LOS
LOC
HDB3/TNDATA
VIO/RNDATA
RClk
RDATA/RPDATA
TClk
TDATA/TPDATA
LP1
LP2
LP3
ALMT
RBC
TBC
PIN DESCRIPTION
Pin #
Symbol
Type
Description
1
LOS
O
Loss of Signal (Active-Low).
This pin is cleared (0) upon loss of the data signal at the re-
ceiver inputs.
Loss of Clock (Active-Low).
This pin is cleared when SD = 1 and LOS= 0, indicating that a
loss of clock has occurred. When LOC= 0, no transitions occur on the RClk and on either
RDATA (for single-rail) or RPDATA and RNDATA (for dual-rail operation) outputs. A valid
clock must be present at BClk for this function to operate properly.
2
LOC
O
3
HDB3/
TNDATA
I
HDB3 Enable/N-Rail Transmit Data.
If SR/DR = 0, this pin is set (1) to insert an HDB3 sub-
stitution code on the transmit side and to remove the substitution code on the receive side. If
SR/DR = 1, this pin is used as the n-rail transmit input data (internal pull-down is included).
4
VIO/
RNDATA
O
Violation/N-Rail Receive Data.
If SR/DR = 0 and HDB3 = 0, bipolar violations on the re-
ceive side input are detected, causing VIO to be set; if HDB3 = 1, HDB3 code violations
cause VIO to be set. If SR/DR =1, this pin is used as the n-rail receive output data.
5
RClk
O
Receive Clock.
Output receive clock signal to the terminal equipment.
6
RDATA/
RPDATA
O
Receive Data/P-Rail Receive Data.
If SR/DR = 0, this pin is used for 2.048 Mbits/s unipo-
lar output data with a 100% duty cycle. If SR/DR = 1, this pin is used as the p-rail receive
output data.
7
TClk
I
Transmit Clock.
Input clock signal (2.048 MHz
80 ppm).
8
TDATA/
TPDATA
LP1
I
Transmit Data/P-Rail Transmit Data.
If SR/DR = 0, this pin is used as 2.048 Mbits/s unipo-
lar input data. If SR/DR = 1, this pin is used as the p-rail transmit input data.
Loopback 1 Enable (Active-Low).
This pin is cleared for a full local loopback (transmit con-
verter output to receive converter input). Most of the transmit and receive analog circuitry is
exercised in this loopback (internal pull-up is included).
9
I
10
LP2
I
Loopback 2 Enable (Active-Low).
This pin is cleared for a remote loopback. In loopback
2, a high on TBC (pin 14) inserts the blue signal (AIS) on the transmit side (internal pull-up is
included).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR-T7295E-1EIP | INTEGRATED LINE RECEIVER |
| XRT7295E | INTEGRATED LINE RECEIVER |
| XR-T7295E-1EIW | INTEGRATED LINE RECEIVER |
| XR-T7295E | INTEGRATED LINE RECEIVER |
| XR-T7295IP | DS3/Sonet STS-1 Integrated Line Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7288IP | 制造商:Exar Corporation 功能描述: 制造商:Exar Corporation 功能描述:DATACOM, PCM TRANSCEIVER, PDIP28 |
| XR-T7288IP | 制造商:EXAR 制造商全稱:EXAR 功能描述:CEPT1 Line Interface |
| XRT7288IW | 制造商:EXAR 制造商全稱:EXAR 功能描述:CEPT1 Line Interface |
| XR-T7288IW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
| XR-T7295 | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/Sonet STS-1 Integrated Line Receiver |
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