參數(shù)資料
型號(hào): XR-T7288
廠商: Exar Corporation
英文描述: CEPT1 Line Interface
中文描述: CEPT1線路接口
文件頁(yè)數(shù): 12/24頁(yè)
文件大?。?/td> 293K
代理商: XR-T7288
XR-T7288
12
Rev. 1.01
A continuous (i.e., ungapped, unswitched) 2.048 MHz
reference clock must be present at BClk to enable the
frequency-acquisition circuitry. However, the receive PLL
will operate even in the absence of a 2.048 MHz clock at
BClk. The 2.048 MHz clock at TClk can also be used to
provide the 2.048 MHz reference at BClk.
Because the clock output of the receive converter is
derived from the ICO, a free-running clock can be present
at the output of the receive converter without data being
present at the input. A shutdown pin (SD) is provided to
block this clock, if desired, to eliminate the free-running
clock upon loss of the input signal.
Both analog and digital methods of loss of signal
detection are used in the XR-T7288 device. The analog
signal detector shown in Figure 6.uses the output of the
receiver peak detector to determine if a signal is present
at T1 and R1. If the input amplitude drops below 0.25 V,
typical, the analog detector output becomes active.
Analog loss-of-signal is registered, at most, several
milliseconds after a drop in signal level, depending on a
variety of factors, such as initial signal amplitude.
Hysteresis (140 mV, typical) is provided in the analog
detector to eliminate LOS chattering. The digital signal
detector counts 0s in the recovered data. If more than 32
consecutive 0s occur, the digital signal detector becomes
active. In normal operation, the detector outputs are
ORed together to form LOS; however, in loopback 1, only
the digital signal detector is used to monitor the looped
signal. Table 2describes the operation of the shutdown,
LOS, and LOC functions in normal operation and in
loopback 1.
The PLL is designed to accommodate large amounts of
input jitter with high power supply rejection for operation in
noisy environments. Low jitter sensitivity to power supply
noise allows compact line-card layouts that employ many
line interfaces on one board. The minimum input jitter
tolerance, as specified in CCITT specification G.823, and
the measured XR-T7288 device jitter tolerance are
shown in Figure 7. Receiver specifications are shown on
page 4. The XR-T7288 device satisfies the CCITT jitter
transfer function requirement of recommendations
G.735 G.739 (see Figure 8.)
Inputs
Outputs
Receive Side
LP1
1
SD
0
ALMT
1
Input Signal
at T1, R1
Active
Loopback 1
Signal
x
LOS
1
LOC
1
Receive
Data
1
Normal
Low
2
RClk
1
Normal
Active LOS
Detectors
Analog & Digital
1
0
1
No Signal
x
0
1
Free-running
ICO
2
Normal
Analog & Digital
1
1
1
Active
x
1
1
Normal
Low
3
Analog & Digital
1
1
1
No Signal
x
0
0
High
Analog & Digital
0
0
1
x
Active
1
1
Normal Loopback
Low
4
Normal Loopback
Digital Only
0
0
1
x
No Signal
0
1
Free-running
ICO
4
Normal Loopback
Digital Only
0
1
1
x
Active
1
1
Normal Loopback
Digital Only
0
1
1
x
No Signal
0
0
Low
High
Digital Only
x
x
0
x
x
0
0
Unaffected
Unaffected
x
Notes:
1
These values apply for single-rail or dual-rail/logic mode 1. For dual-rail/logic mode 2, all logic-level outputs except for looped
back data are the inverse of that shown above.
2
Activated by analog loss-of-signal (LOS) detection.
3
Digital LOS detection forces receive data low . Analog LOS detection merely forces receive data to stop transitions; receive data
will be forced either high or low with analog LOS detection.
4
All-0s looped back data, no HDB3 operation. Sufficiently sparse looped back data (not HDB3 encoded) also causes the receive
ICO to free run; therefore, properly timed loopback data is not guaranteed.
Table 2. Shutdown LOS and LOC Truth~Table
x = don’t care.
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