參數(shù)資料
型號(hào)： XR-T7288
廠商： Exar Corporation
英文描述： CEPT1 Line Interface
中文描述： CEPT1線路接口
文件頁(yè)數(shù)： 11/24頁(yè)
文件大?。?/td> 293K
代理商： XR-T7288
XR-T7288
11
Rev. 1.01
Figure 6. XR-T7288 Analog Block Diagram
Analog
Signal
Detector
Receiver
Analog
Input
PDATA
NDATA
M
U
X
Data/Clock
Recovery
RP
RN
RClk
Digital
Signal
Detector
Transmit
and
Receive
Logic
TClk
TP
TN
Clock
Multiplier
2
Timing
Signals
High Speed
D/A
ZS
Transmit
Output
Drivers
T1
R1
T2
R2
RDATA/RPDATA
VIO/RNDATA
RClk
TDATA/TPDATA
HDB3/TNDATA
TClk
LP1
LOS
SD
RECEIVE CONVERTER
The receive converter accepts bipolar input signals (T1,
R1), with a maximum of 6dB loss at 1024kHz, through the
interconnection cable. The received signal is rectified
while the amplitude and rise time are restored. These
input signals are peak-detected and sliced by the receiver
front end, producing the digital signals PDATA and
NDATA (see Figure 6.) Receive decision levels are
automatically adjusted to be 50% of peak-to-zero signal
levels. The timing is extracted by means of PLL circuitry
that locks an internal, free-running, current-controlled
oscillator (ICO) to the 2.048MHz component.
The PLL employs a 3-state phase detector and a
low-voltage/temperature coefficient ICO. The ICO
free-running frequency is trimmed to within 2.5% of the
data rate at wafer probe, with V
DD
= 5.0 V and TA = 25
°
C.
For all operating conditions (see Operating Conditions
section), the free-running oscillator frequency deviates
from the data rate by less than
problem of harmonic lock.
7%, alleviating the
For robust operation, the PLL is augmented with a
frequency-acquisition capability. This feature detects if
the recovered PLL clock (RClk) deviates by more than
+1.7/-1.6% in frequency from a 2.048 MHz reference
clock, which must be provided at BClk. If the RClk
frequency is not within the prescribed range of the BClk
frequency, the XR-T7288 device enters a training mode in
which receive input data is disconnected from the PLL,
and the RClk frequency is steered to equal the BClk
frequency. After frequency acquisition is completed, the
PLL reconnects to receive input data to acquire proper
phase-lock and timing of RClk with respect to the
incoming T1, R1 data. Valid data is available when proper
phase-lock has been achieved.
The frequency acquisition circuitry is intended to avoid
improper harmonic locking during start-up situations,
such as power-up or data interruption. Once the
XR-T7288 device is phase-locked to data, the
frequency-acquisition mode will not be activated.
相關(guān)PDF資料
PDF描述
XR-T7295E-1EIP INTEGRATED LINE RECEIVER
XRT7295E INTEGRATED LINE RECEIVER
XR-T7295E-1EIW INTEGRATED LINE RECEIVER
XR-T7295E INTEGRATED LINE RECEIVER
XR-T7295IP DS3/Sonet STS-1 Integrated Line Receiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT7288IP 制造商:Exar Corporation 功能描述: 制造商:Exar Corporation 功能描述:DATACOM, PCM TRANSCEIVER, PDIP28
XR-T7288IP 制造商:EXAR 制造商全稱:EXAR 功能描述:CEPT1 Line Interface
XRT7288IW 制造商:EXAR 制造商全稱:EXAR 功能描述:CEPT1 Line Interface
XR-T7288IW 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver
XR-T7295 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/Sonet STS-1 Integrated Line Receiver
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