參數(shù)資料
型號： XQ4010E-3HQ208N
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Array (FPGA)
中文描述： FPGA, 400 CLBS, 7000 GATES, 125 MHz, PQFP208
封裝： PLASTIC, QFP-208
文件頁數(shù)： 36/36頁
文件大小： 294K
代理商： XQ4010E-3HQ208N
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
1-800-255-7778
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XQ4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000E/EX devices unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol
Write Operation Description
Size
-3
-4
Units
Min
Max
Min
Max
TWCS
Address write cycle time (clock K period)
16x2
14.4
-
15.0
-
ns
TWCTS
32x1
14.4
-
15.0
-
ns
TWPS
Clock K pulse width (active edge)
16x2
7.2
1 ms
7.5
1 ms
ns
TWPTS
32x1
7.2
1 ms
7.5
1 ms
ns
TASS
Address setup time before clock K
16x2
2.4
-
2.8
-
ns
TASTS
32x1
2.4
-
2.8
-
ns
TAHS
Address hold time after clock K
16x2
0
-
0
-
ns
TAHTS
32x1
0
-
0
-
ns
TDSS
DIN setup time before clock K
16x2
3.2
-
3.5
-
ns
TDSTS
32x1
1.9
-
2.5
-
ns
TDHS
DIN hold time after clock K
16x2
0
-
0
-
ns
TDHTS
32x1
0
-
0
-
ns
TWSS
WE setup time before clock K
16x2
2.0
-
2.2
-
ns
TWSTS
32x1
2.0
-
2.2
-
ns
TWHS
WE hold time after clock K
16x2
0
-
0
-
ns
TWHTS
32x1
0
-
0
-
ns
TWOS
Data valid after clock K
16x2
8.8
-
10.3
ns
TWOTS
32x1
10.3
-
11.6
ns
Notes:
1.
Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
2.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol
Write Operation Description
Size(1)
-3
-4
Units
Min
Max
Min
Max
TWCDS
Address write cycle time (clock K period)
16x1
14.4
15.0
ns
TWPDS
Clock K pulse width (active edge)
16x1
7.2
1 ms
7.5
1 ms
ns
TASDS
Address setup time before clock K
16x1
2.5
-
2.8
-
ns
TAHDS
Address hold time after clock K
16x1
0
-
0
-
ns
TDSDS
DIN setup time before clock K
16x1
2.5
-
2.2
-
ns
TDHDS
DIN hold time after clock K
16x1
0
-
0
-
ns
TWSDS
WE setup time before clock K
16x1
1.8
-
2.2
-
ns
TWHDS
WE hold time after clock K
16x1
0
-
0.3
-
ns
TWODS
Data valid after clock K
16x1
-
7.8
-
10.0
ns
Notes:
1.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.
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