參數(shù)資料
型號(hào)： XQ4010E-3HQ208N
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Array (FPGA)
中文描述： FPGA, 400 CLBS, 7000 GATES, 125 MHz, PQFP208
封裝： PLASTIC, QFP-208
文件頁數(shù)： 34/36頁
文件大?。?/td> 294K
代理商： XQ4010E-3HQ208N
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
1-800-255-7778
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XQ4000E CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4000E devices unless otherwise noted.
Symbol
Description
-3
-4
Units
Min
Max
Min
Max
Combinatorial Delays
TILO
F/G inputs to X/Y outputs
-
2.01
-
2.7
ns
TIHO
F/G inputs via H to X/Y outputs
-
4.3
-
4.7
ns
THH0O
C inputs via SR through H to X/Y outputs
-
3.3
-
4.1
ns
THH1O
C inputs via H to X/Y outputs
-
3.6
-
3.7
ns
THH2O
C inputs via DIN through H to X/Y outputs
-
3.6
-
4.5
ns
CLB Fast Carry Logic
TOPCY
Operand inputs (F1, F2, G1, G4) to COUT
-2.6
-3.2
ns
TASCY
Add/Subtract input (F3) to COUT
-4.4
-5.5
ns
TINCY
Initialization inputs (F1, F3) to COUT
-1.7
ns
TSUM
CIN through function generators to X/Y outputs
-
3.3
-
3.8
ns
TBYP
CIN to COUT, bypass function generators
-
0.7
-
1.0
ns
Sequential Delays
TCKO
Clock K to outputs Q
-
2.8
-
3.7
ns
Setup Time before Clock K
TICK
F/G inputs
3.0
-
4.0
-
ns
TIHCK
F/G inputs via H
4.6
-
6.1
-
ns
THH0CK
C inputs via H0 through H
3.6
-
4.5
-
ns
THH1CK
C inputs via H1 through H
4.1
-
5.0
-
ns
THH2CK
C inputs via H2 through H
3.8
-
4.8
-
ns
TDICK
C inputs via DIN
2.4
-
3.0
-
ns
TECCK
C inputs via EC
3.0
-
4.0
-
ns
TRCK
C inputs via S/R, going Low (inactive)
4.0
-
4.2
-
ns
TCCK
CIN input via F/G
2.1
-
2.5
-
ns
TCHCK
CIN input via F/G and H
3.5
-
4.2
-
ns
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