參數(shù)資料
型號(hào)： XQ4010E-3HQ208N
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Array (FPGA)
中文描述： FPGA, 400 CLBS, 7000 GATES, 125 MHz, PQFP208
封裝： PLASTIC, QFP-208
文件頁(yè)數(shù)： 22/36頁(yè)
文件大?。?/td> 294K
代理商： XQ4010E-3HQ208N
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
Product Specification
1-800-255-7778
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XQ4028EX IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4000EX devices unless otherwise noted.
Symbol
Description
-4
Units
Min
Clocks
TOKIK
Delay from FCL enable (OK) active to IFF clock (IK) active edge
3.2
ns
Propagation Delays
TPID
Pad to I1, I2
2.2
ns
TPLI
Pad to I1, I2 via transparent input latch, no delay
3.8
ns
TPPLI
Pad to I1, I2 via transparent input latch, partial delay
13.3
ns
TPDLI
Pad to I1, I2 via transparent input latch, full delay
18.2
ns
TPFLI
Pad to I1, I2 via transparent FCL and input latch, no delay
5.3
ns
TPPFLI
Pad to I1, I2 via transparent FCL and input latch, partial delay
13.6
ns
Propagation Delays (TTL Inputs)
TIKRI
Clock (IK) to I1, I2 (flip-flop)
3.0
ns
TIKLI
Clock (IK) to I1, I2 (latch enable, active Low)
3.2
ns
TOKLI
FCL enable (OK) active edge to I1, I2 (via transparent standard input latch)
6.2
ns
Global Set/Reset
TMRW
Minimum GSR pulse width
13.0
ns
TRRI
Delay from GSR input to any Q
22.8
ns
Notes:
1.
FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch
2.
3.
For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold
tables on page 70.
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