參數(shù)資料
型號: XPC862PZP50
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC PROCESSOR, PBGA357
封裝: PLASTIC, BGA-357
文件頁數(shù): 23/82頁
文件大小: 530K
代理商: XPC862PZP50
MOTOROLA
MPC862 Family Hardware Specications
3
Features
— Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
— Optional statistical cell counters per PHY
— Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode.
— Supports full-duplex UTOPIA master (ATM side) operation using a “split” bus
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Operates at up to 80 MHz
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to DRAM, SIMMS, SRAM, EPROMs, ash EPROMs, and other memory
devices.
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
Fast Ethernet controller (FEC)
— Simultaneous MII (100Base-T) and UTOPIA operation when using the UTOPIA multiplexed
bus.
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Interrupts
— Seven external interrupt request (IRQ) lines
— 12 port pins with interrupt capability
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