參數(shù)資料
型號： XPC862PZP50
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 50 MHz, RISC PROCESSOR, PBGA357
封裝： PLASTIC, BGA-357
文件頁數(shù)： 12/82頁
文件大小： 530K
代理商： XPC862PZP50
2
MPC862 Family Hardware Specications
MOTOROLA
Features
controller (I2C) channel. The memory controller has been enhanced, enabling the MPC862 to support any
type of memory, including high-performance memories and new types of DRAMs. A PCMCIA socket
controller supports up to two sockets. A real-time clock has also been integrated.
Table 1 shows the functionality supported by the members of the MPC862 family.
Unless otherwise specied, the PowerQUICC unit is referred to as the MPC862 in this document.
Part II Features
The following list summarizes the key MPC862 features:
Embedded single-issue, 32-bit MPC8xx core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
– 16-Kbyte instruction caches (MPC862P and MPC862DP) are four-way, set-associative
with 256 sets; 4-Kbyte instruction caches (MPC862T, MPC862SR, and MPC862DT) are
two-way, set-associative with 128 sets.
– 8-Kbyte data caches (MPC862P and MPC862DP) are two-way, set-associative with 256
sets; 4-Kbyte data caches (MPC862T, MPC862SR, and MPC862DT) are two-way,
set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
— Advanced on-chip-emulation debug mode
The MPC862 provides enhanced ATM functionality over that of the MPC860SAR. The MPC862
adds major new features available in “enhanced SAR” (ESAR) mode, including the following:
— Multiple APC priority levels available to support a range of trafc pace requirements
— Port-to-port switching capability without the need for RAM-based microcode
Table 1. MPC862 Family Functionality
Part
Cache
Ethernet
SCC
Instruction
Cache
Data Cache
10T
10/100
MPC862DT
4 Kbyte
Up to 2
1
2
MPC862DP
16 Kbyte
8 Kbyte
Up to 2
1
2
MPC862SR
4 Kbyte
Up to 4
—
4
MPC862T
4 Kbyte
Up to 4
1
4
MPC862P
16 Kbyte
8 Kbyte
Up to 4
1
4
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