參數(shù)資料
型號: XCV812E-8BG560C
廠商: Xilinx Inc
文件頁數(shù): 8/118頁
文件大?。?/td> 0K
描述: IC FPGA 1.8V C-TEMP 560-MBGA
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-E EM
LAB/CLB數(shù): 4704
邏輯元件/單元數(shù): 21168
RAM 位總計: 1146880
輸入/輸出數(shù): 404
門數(shù): 254016
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 560-LBGA,金屬
供應(yīng)商設(shè)備封裝: 560-MBGA(42.5x42.5)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-4 (v3.0) March 21, 2014
Module 4 of 4
29
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
2
IO_L97P
N25
2
IO_L97N
N27
2
IO_VREF_L98P_YY
N30
2
IO_D3_L98N_YY
P21
2
IO_L99P_YY
N26
2
IO_L99N_YY
P28
2
IO_L100P_Y
P29
2
IO_L100N_Y
N24
2
IO_L101P
P22
2
IO_L101N
R26
2
IO_VREF_2_L102P
P25
2
IO_L102N
R29
2
IO_L104P
R25
2
IO_L104N
T30
2
IO_L106P
R24
3IO
T24
3IO
V24
3IO
Y21
3IO
Y27
3IO
AB27
3IO
AF28
3IO
AG30
3
IO_L106N
U29
3
IO_L107P
R22
3
IO_L107N
T27
3
IO_L108P
R23
3
IO_L108N
T28
3
IO_L109P
T21
3
IO_VREF_L109N
T25
3
IO_L110P
U28
3
IO_L110N
U30
3
IO_L111P_Y
T23
3
IO_L111N_Y
U27
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
3
IO_L112P_YY
U25
3
IO_L112N_YY
V27
3
IO_D4_L113P_YY
U24
3
IO_VREF_L113N_YY
V29
3
IO_L114P
W30
3
IO_L114N
U22
3
IO_L115P
U21
3
IO_L115N
W29
3
IO_L116P_YY
V26
3
IO_L116N_YY
W27
3
IO_L117P_Y
W26
3
IO_VREF_L117N_Y
Y29
3
IO_L118P
W25
3
IO_L118N
Y30
3
IO_L120P
AA30
3
IO_L120N
W24
3
IO_L121P_Y
AA29
3
IO_L121N_Y
V20
3
IO_L123P_YY
Y26
3
IO_D5_L123N_YY
AB30
3
IO_D6_L124P_YY
V21
3
IO_VREF_L124N_YY
AA28
3
IO_L125P
Y25
3
IO_L125N
AA27
3
IO_L126P
W22
3
IO_L126N
Y23
3
IO_L127P
Y24
3
IO_VREF_L127N
AB28
3
IO_L128P
AC30
3
IO_L128N
AA25
3
IO_L129P_Y
W21
3
IO_L129N_Y
AA24
3
IO_L130P_YY
AB26
3
IO_L130N_YY
AD30
Table 5:
FG900 Fine-Pitch BGA Package — XCV812E
Bank
Description
Pin
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