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參數(shù)資料
| 型號(hào)： | XCV812E-8BG560C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 70/118頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 560-MBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 4704 |
| 邏輯元件/單元數(shù)： | 21168 |
| RAM 位總計(jì)： | 1146880 |
| 輸入/輸出數(shù)： | 404 |
| 門數(shù)： | 254016 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 560-LBGA，金屬 |
| 供應(yīng)商設(shè)備封裝： | 560-MBGA（42.5x42.5） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
51
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Revision History
The following table shows the revision history for this document.
IOBUFDS_LD_LVDS
D, T, G
IO, IOB
Q
IOBUFDS_LDE_LVDS
D, T, GE, G
IO, IOB
Q
IOBUFDS_LDC_LVDS
D, T, G, CLR
IO, IOB
Q
IOBUFDS_LDCE_LVDS
D, T, GE, G, CLR
IO, IOB
Q
IOBUFDS_LDP_LVDS
D, T, G, PRE
IO, IOB
Q
IOBUFDS_LDPE_LVDS
D, T, GE, G, PRE
IO, IOB
Q
Date
Version
Revision
03/23/2000
1.0
Initial Xilinx release.
08/01/2000
1.1
Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.
Reformatted to adhere to corporate documentation style guidelines. Minor changes in
BG560 pin-out table.
09/19/2000
1.2
In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no
longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.
Min values added to Virtex-E Electrical Characteristics tables.
11/20/2000
1.3
Updated speed grade -8 numbers in Virtex-E Electrical Characteristics tables
(Module 3).
Updated minimums in Table 11 (Module 2), and added notes to Table 12 (Module 2).
Added to note 2 of Absolute Maximum Ratings (Module 3).
Changed all minimum hold times to –0.4 for Global Clock Set-Up and Hold for LVTTL
Standard, with DLL (Module 3).
Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters (Module 3).
04/02/2001
1.4
In Table 4, FG676 Fine-Pitch BGA — XCV405E, pin B19 is no longer labeled as VREF,
and pin G16 is now labeled as VREF.
Updated values in Virtex-E Switching Characteristics tables.
Converted data sheet to modularized format.
04/19/2001
1.5
Modified Figure 30, which shows “DLL Generation of 4x Clock in Virtex-E Devices.”
07/23/2001
1.6
Made minor edits to text under Configuration.
11/16/2001
2.0
Added warning under Configuration section that attempting to load an incorrect
bitstream causes configuration to fail and can damage the device.
07/17/2002
2.1
Data sheet designation upgraded from Preliminary to Production.
09/10/2002
2.2
11/19/2002
2.3
Added clarification in the Boundary Scan section.
Removed last sentence regarding deactivation of duty-cycle correction in Duty Cycle
Correction Property section.
03/21/2014
3.0
This product is obsolete/discontinued per XCN12026.
Table 44:
Bidirectional I/O Library Macros (Continued)
Name
Inputs
Bidirectional
Outputs
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-8BG560I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG676C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-8BG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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