參數資料
型號： XCV812E-8BG560C
廠商： Xilinx Inc
文件頁數： 23/118頁
文件大?。?/td> 0K
描述： IC FPGA 1.8V C-TEMP 560-MBGA
產品變化通告： FPGA Family Discontinuation 18/Apr/2011
標準包裝： 1
系列： Virtex®-E EM
LAB/CLB數： 4704
邏輯元件/單元數： 21168
RAM 位總計： 1146880
輸入/輸出數： 404
門數： 254016
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 560-LBGA，金屬
供應商設備封裝： 560-MBGA（42.5x42.5）
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
8
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
DLL provides four quadrature phases of the source clock,
and can double the clock or divide the clock by 1.5, 2, 2.5, 3,
4, 5, 8, or 16.
The DLL also operates as a clock mirror. By driving the output
from a DLL off-chip and then back on again, the DLL can be
used to de-skew a board level clock among multiple devices.
In order to guarantee that the system clock is operating cor-
rectly prior to the FPGA starting up after configuration, the
DLL can delay the completion of the configuration process
until after it has achieved lock.
For more information about DLL functionality, see the
Design Consideration section of the data sheet.
Boundary Scan
Virtex-E devices support all the mandatory boundary-scan
instructions specified in the IEEE standard 1149.1. A Test
Access Port (TAP) and registers are provided that imple-
ment the EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions. The TAP
also supports two internal scan chains and configura-
tion/readback of the device.
The JTAG input pins (TDI, TMS, TCK) do not have a VCCO
requirement, and operate with either 2.5 V or 3.3 V input
signalling levels. The output pin (TDO) is sourced from the
VCCO in bank 2, and for proper operation of LVTTL 3.3 V
levels, the bank should be supplied with 3.3 V.
Boundary-scan operation is independent of individual IOB
configurations, and unaffected by package type. All IOBs,
including un-bonded ones, are treated as independent
3-state bidirectional pins in a single scan chain. Retention of
the bidirectional test capability after configuration facilitates
the testing of external interconnections, provided the user
design or application is turned off.
Table 6 lists the boundary-scan instructions supported in
Virtex-E FPGAs. Internal signals can be captured during
EXTEST by connecting them to un-bonded or unused IOBs.
They can also be connected to the unused outputs of IOBs
defined as unidirectional input pins.
Before the device is configured, all instructions except
USER1 and USER2 are available. After configuration, all
instructions are available. During configuration, it is recom-
mended that those operations using the boundary-scan
register (SAMPLE/PRELOAD, INTEST, EXTEST) not be
performed.
In addition to the test instructions outlined above, the
boundary-scan circuitry can be used to configure the
FPGA, and also to read back the configuration data.
Figure 10: DLL Locations
XCVE_0010
DLLDLL
Primary DLLs
Secondar
y
DLLs
Secondar
y
DLLs
DLLDLL
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相關代理商/技術參數
參數描述
XCV812E-8BG560I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-8BG676C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-8BG676I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-8BG900C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV812E-8BG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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