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參數(shù)資料
| 型號： | XCV405E-8FG676C |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 242K |
| 代理商： | XCV405E-8FG676C |
Virtex
-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v2.1) February 1, 2002
1-800-255-7778Module 3 of 4
9
R
Calculation of T
ioop
as a Function of Capacitance
T
ioop
is the propagation delay from the O Input of the IOB to the
pad. The values for T
ioop
are based on the standard capacitive
load (Csl) for each I/O standard as listed in
Table 2
.
Table 2:
Constants for Use in Calculation of T
ioop
For other capacitive loads, use the formulas below to calcu-
late the corresponding T
ioop
.
T
ioop
= T
ioop
+ T
opadjust
+
(C
load
–
C
sl
) * fl
where:
T
opadjust
is reported above in the Output Delay
Adjustment section.
C
load
is the capacitive load for the design.
Standard
Csl
(pF)
fl
(ns/pF)
LVTTL Fast Slew Rate, 2mA drive
35
0.41
LVTTL Fast Slew Rate, 4mA drive
35
0.20
LVTTL Fast Slew Rate, 6mA drive
35
0.13
LVTTL Fast Slew Rate, 8mA drive
35
0.079
LVTTL Fast Slew Rate, 12mA drive
35
0.044
LVTTL Fast Slew Rate, 16mA drive
35
0.043
LVTTL Fast Slew Rate, 24mA drive
35
0.033
LVTTL Slow Slew Rate, 2mA drive
35
0.41
LVTTL Slow Slew Rate, 4mA drive
35
0.20
LVTTL Slow Slew Rate, 6mA drive
35
0.10
LVTTL Slow Slew Rate, 8mA drive
35
0.086
LVTTL Slow Slew Rate, 12mA drive
35
0.058
LVTTL Slow Slew Rate, 16mA drive
35
0.050
LVTTL Slow Slew Rate, 24mA drive
35
0.048
LVCMOS2
35
0.041
LVCMOS18
35
0.050
PCI 33 MHZ 3.3 V
10
0.050
PCI 66 MHz 3.3 V
10
0.033
GTL
0
0.014
GTL+
0
0.017
HSTL Class I
20
0.022
HSTL Class III
20
0.016
HSTL Class IV
20
0.014
SSTL2 Class I
30
0.028
SSTL2 Class II
30
0.016
SSTL3 Class I
30
0.029
SSTL3 Class II
30
0.016
CTT
20
0.035
AGP
10
0.037
Notes:
1.
I/O parameter measurements are made with the capacitance
values shown above. See the
Application Examples
for
appropriate terminations.
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
2.
Table 3:
Delay Measurement Methodology
Standard
V
L1
V
H1
Meas.
Point
V
REF
(Typ)
2
LVTTL
0
3
1.4
-
LVCMOS2
0
2.5
1.125
-
PCI33_3
Per PCI Spec
-
PCI66_3
Per PCI Spec
-
GTL
V
REF
–
0.2
V
REF
+0.2
V
REF
0.80
GTL+
V
REF
–
0.2
V
REF
+0.2
V
REF
1.0
HSTL Class I
V
REF
–
0.5
V
REF
+0.5
V
REF
0.75
HSTL Class III
V
REF
–
0.5
V
REF
+0.5
V
REF
0.90
HSTL Class IV
V
REF
–
0.5
V
REF
+0.5
V
REF
0.90
SSTL3 I & II
V
REF
–
1.0
V
REF
+1.0
V
REF
1.5
SSTL2 I & II
V
REF
–
0.75
V
REF
+0.75
V
REF
1.25
CTT
V
REF
–
0.2
V
REF
+0.2
V
REF
1.5
AGP
V
REF
–
(0.2xV
CCO
)
V
REF
+
(0.2xV
CCO
)
V
REF
Per
AGP
Spec
LVDS
1.2
–
0.125
1.2 + 0.125
1.2
LVPECL
1.6
–
0.3
1.6 + 0.3
1.6
Notes:
1.
2.
Input waveform switches between V
L
and V
H
.
Measurements are made at V
(Typ), Maximum, and
Minimum. Worst-case values are reported.
I/O parameter measurements are made with the capacitance
values shown in
Table 2
. See the
Application Examples
for
appropriate terminations.
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV405E-8FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV50 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
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