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參數(shù)資料
| 型號： | XCV405E-8FG676C |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 242K |
| 代理商： | XCV405E-8FG676C |
Virtex
-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v2.1) February 1, 2002
1-800-255-7778Module 3 of 4
5
R
Virtex-E Switching Characteristics
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all Virtex-E
devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in
‘‘
IOB Input Switching Characteristics Standard Adjustments
’’
on page 6
.
Speed Grade
2
Units
Description
1
Symbol
Device
Min
3
-8
-7
-6
Propagation Delays
Pad to I output, no delay
T
IOPI
All
0.43
0.8
0.8
0.8
ns, max
Pad to I output, with delay
T
IOPID
XCV405E
0.51
1.0
1.0
1.0
ns, max
XCV812E
0.55
1.1
1.1
1.1
ns, max
Propagation Delays
Pad to output IQ via transparent latch,
no delay
T
IOPLI
All
0.75
1.4
1.5
1.6
ns, max
Pad to output IQ via transparent latch,
with delay
T
IOPLID
XCV405E
1.55
3.5
3.6
3.7
ns, max
XCV812E
1.55
3.5
3.6
3.7
ns, max
Clock CLK to output IQ
T
IOCKIQ
All
0.18
0.4
0.7
0.7
ns, max
Setup and Hold Times with respect to Clock at IOB Input Register
Pad, no delay
T
IOPICK
/
T
IOICKP
All
0.69 / 0
1.3 / 0
1.4 / 0
1.5 / 0
ns, min
Pad, with delay
T
IOPICKD
/
T
IOICKPD
XCV405E
1.49 / 0
3.4 / 0
3.5 / 0
3.5 / 0
ns, min
XCV812E
1.49 / 0
3.4 / 0
3.5 / 0
3.5 / 0
ns, min
ICE input
T
IOICECK
/
T
IOCKICE
T
IOSRCKI
All
0.28 /
0.0
0.55 /
0.01
0.7 /
0.01
0.7 /
0.01
ns, min
SR input (IFF, synchronous)
All
0.38
0.8
0.9
1.0
ns, min
Set/Reset Delays
SR input to IQ (asynchronous)
T
IOSRIQ
T
GSRQ
All
0.54
1.1
1.2
1.4
ns, max
GSR to output IQ
All
3.88
7.6
8.5
9.7
ns, max
Notes:
1.
A Zero
“
0
”
Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed
“
best-case
”
, but
if a
“
0
”
is listed, there is no positive hold time.
Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see
Table 3
.
The numbers for Min are
Advance
product specification numbers.
2.
3.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV405E-8FG676I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-8FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV50 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV50-4BG256C | 功能描述:IC FPGA 2.5V C-TEMP 256-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計:16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
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