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參數(shù)資料
| 型號： | XCS20XL-5PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 7/83頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 3.3V C-TEMP HP 208PQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 26/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 400 |
| 邏輯元件/單元數(shù)： | 950 |
| RAM 位總計： | 12800 |
| 輸入/輸出數(shù)： | 160 |
| 門數(shù)： | 20000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
15
Product Specification
R
Product Obsolete/Under Obsolescence
WCLK can be configured as active on either the rising edge
(default) or the falling edge. While the WCLK input to the
RAM accepts the same signal as the clock input to the asso-
ciated CLB’s flip-flops, the sense of this WCLK input can be
inverted with respect to the sense of the flip-flop clock
inputs. Consequently, within the same CLB, data at the
RAM SPO line can be stored in a flip-flop with either the
same or the inverse clock polarity used to write data to the
RAM.
The WE input is active High and cannot be inverted within
the CLB.
Allowing for settling time, the data on the SPO output
reflects the contents of the RAM location currently
addressed. When the address changes, following the asyn-
chronous delay TILO, the data stored at the new address
location will appear on SPO. If the data at a particular RAM
address is overwritten, after the delay TWOS, the new data
will appear on SPO.
Dual-Port Mode
In dual-port mode, the function generators (F-LUT and
G-LUT) are used to create a 16 x 1 dual-port memory. Of
the two data ports available, one permits read and write
operations at the address specified by A[3:0] while the sec-
ond provides only for read operations at the address speci-
fied independently by DPRA[3:0]. As a result, simultaneous
read/write operations at different addresses (or even at the
same address) are supported.
The functional organization of the 16 x 1 dual-port RAM is
shown in Figure 14. The dual-port RAM signals and the
Figure 13: Data Write and Access Timing for RAM
DS060_13_080400
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
TDSS
TDHS
TASS
TAHS
TWSS
TWPS
TWHS
TWOS
TILO
Figure 14: Logic Diagram for the Dual-Port RAM
WE
WCLK
A[3:0]
D
4
SPO
DPRA[3:0]
INPUT
REGISTER
WRITE
R
O
W
SELECT
WRITE
CONTROL
READ
OUT
16 x 1
RAM
READ
R
O
W
SELECT
DS060_14_043001
DPO
WRITE
R
O
W
SELECT
WRITE
CONTROL
READ
OUT
16 x 1
RAM
READ
R
O
W
SELECT
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