- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4058 > XCS20XL-5PQ208C (Xilinx Inc)IC FPGA 3.3V C-TEMP HP 208PQFP PDF資料下載
參數(shù)資料
| 型號： | XCS20XL-5PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 33/83頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 3.3V C-TEMP HP 208PQFP |
| 產(chǎn)品變化通告： | Product Discontinuation 26/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 400 |
| 邏輯元件/單元數(shù)： | 950 |
| RAM 位總計： | 12800 |
| 輸入/輸出數(shù)： | 160 |
| 門數(shù)： | 20000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
39
Product Specification
R
Product Obsolete/Under Obsolescence
Readback Abort
When the Readback Abort option is selected, a High-to-Low
transition on RDBK.TRIG terminates the Readback opera-
tion and prepares the logic to accept another trigger.
After an aborted Readback, additional clocks (up to one
Readback clock per configuration frame) may be required to
re-initialize the control logic. The status of Readback is indi-
cated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.
Clock Select
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If Readback
must be inhibited for security reasons, the Readback control
nets are simply not connected. RDBK.CLK is located in the
lower right chip corner.
Violating the Maximum High and Low Time
Specification for the Readback Clock
The Readback clock has a maximum High and Low time
specification. In some cases, this specification cannot be
met. For example, if a processor is controlling Readback, an
interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
specification.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mech-
anism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the following
frame. This loading process is dynamic, and is the source of
the maximum High and Low time requirements.
Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the Readback data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it can be shifted out just
like a regular shift register.
The user must precisely calculate the location of the Read-
back data relative to the frame. The system must keep track
of the position within a data frame, and disable interrupts
before frame boundaries. Frame lengths and data formats
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 65801-061LF | CLINCHER RECEPTACLE ASSY GOLD |
| MPC862TCZQ66B | IC MPU PWRQUICC 66MHZ 357-PBGA |
| ABB92DHBT-S329 | CONN EDGECARD 184POS R/A .050 SL |
| MPC860PCZQ50D4 | IC MPU POWERQUICC 50MHZ 357PBGA |
| MPC8360ECZUAGDGA | IC MPU POWERQUICC II PRO 740TBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS20XL-5PQ208I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20XL-5PQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20XL-5PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS20XL-5PQ256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS20XL-5PQ256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。