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參數(shù)資料
| 型號(hào)： | XC95108 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD(在系統(tǒng)復(fù)雜可編程邏輯器件) |
| 中文描述： | 在系統(tǒng)可編程的CPLD（在系統(tǒng)復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 74K |
| 代理商： | XC95108 |
XAPP073 January, 1998 (Version 1.3)
2-25
2
Figure 7: Driving 3.3 volt and 5.0 volt Components
High Speed Design Considerations
XC9500 CPLDs are offered with pin-to-pin delays as fast as
5 ns, and the actual speed may be faster. Therefore, addi-
tional care should be taken to minimize noise so that
adjoining devices will operate properly.
Many high speed designs also require high current drive
outputs for handling capacitive loads. XC9500 CPLDs pro-
vide 24 mA drivers to eliminate the need for additional buff-
ering and therefore the designer needs to manage the total
current being switched to minimize possible ground rise
problems.
As with other high speed logic devices, XC9500 CPLDs
should use low inductance capacitors located as close as
possible to the V
CC
and GND pins on a PC board. Care
should be taken to mount the devices so that the PC board
interconnect traces are as close as possible to the target
signal destinations.
PC Board Layout Checklist:
Complying with the following checklist assures a successful
design with XC9500 CPLDs:
1. Tie unused inputs to ground.
2. Locate XC9500 CPLDs near the devices they drive (or
are driven by) to minimize transmission line effects.
3. Use wide spacing between fast signal lines (particularly
clocks) to minimize crosstalk.
4. Place power pins (V
CC
and GND) on separate printed
circuit board planes. Fast signals should reside on a dif-
ferent plane.
5. Decouple the device V
CC
input with a 0.1
μ
f capacitor
connected to the nearest ground plane. Low inductance,
surface mounted capacitors are recommended.
6. Decouple the printed circuit board power inputs with 0.1
μ
f ceramic (high frequency) and 100
μ
f electrolytic (low
frequency) filter capacitors.
7. Connect all device ground pins together.
8. Avoid using sockets to attach XC9500 CPLDs to the
PCB. Direct soldered connection minimizes inductance
and reduces ground rise. XC9500 CPLDs are specifi-
cally designed for direct PCB attachment.
Managing Ground Rise
Designers must also be aware of additional factors that can
affect the performance of fast, high-current drive systems.
Possible voltage rise on device ground pins can affect the
driven output levels and be sensed by the switching CPLD.
Figure 8
shows how ground rise is typically observed. In
this setup, multiple outputs are switched with a control vari-
able, while one output is constantly being driven low and
observed.
Figure 8: Ground Rise Test
As the multiple outputs switch, their in-rushing current con-
verges at the ground pins of the device. Lead impedance
causes the reference ground to develop a voltage higher
than that which occurs before switching. The result is that
the static output being observed also develops an observ-
able voltage swing.
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
X5873
CPLD 3.3 V I/O
5 V and 3.3 V Logic
Input and Output Breakdown
V
IH
Max 5.5 V (TTL)
V
IH
Max 3.6 V (LVTTL)
V
IH
Min 2.0 V
V
IL
Max 0.8 V
V
OL
Max 0.4 V
V
OH
Min 2.4 V
V
OH
Max 3.6 V
Control
High
CPLD
Switching
Outputs
Static Output
(Observed)
X5858
tpd
Control Input
Switching Outputs
Static Output
Ground Rise
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| XC95108-10PC84I | 功能描述:IC CPLD 108 MCELL I-TEMP 84PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:XC9500 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| XC95108-10PCG84C | 制造商:Xilinx 功能描述:XLXXC95108-10PCG84C IC SYSTEM GATE |
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| XC95108-10PQ100C0586 | 制造商:Xilinx 功能描述: |
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