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參數(shù)資料
| 型號： | XC95108 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD(在系統(tǒng)復(fù)雜可編程邏輯器件) |
| 中文描述： | 在系統(tǒng)可編程的CPLD（在系統(tǒng)復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 74K |
| 代理商： | XC95108 |
Designing with XC9500 CPLDs
2-24
XAPP073 January, 1998 (Version 1.3)
Practical Considerations for XC9500
Designs
By following a few simple rules, XC9500 devices can easily
interface with systems using 3.3 volt and 5 volt devices.
Also, these devices behave much better if standard high
performance printed circuit board techniques are used (as
with all high-speed devices) so a small checklist is provided
here for those rules.
Mixed Voltage Operation
XC9500 CPLDs support mixed voltage systems combining
both 3.3 volt and 5 volt components as shown in
Figure 6
.
The XC9500 family contains both logic and level shifting
functions in a single programmable device. This eliminates
the need for discrete level translation buffers. The XC9500
devices feature split power supply rails. The internal core
logic always runs at 5 volts for the fastest possible perfor-
mance. The output buffers can be powered by either 5 volts
or 3.3 volts by connecting the I/O V
CC
to a 3.3 volt or 5 volt
supply. True TTL compatibility allows XC9500 CPLDs to
drive and be driven by any combination of 3.3 and 5 volt
logic without any performance penalty, even when the I/O
V
CC
pins are powered by 3.3 volts.
The XC9500 I/O structure is shown in
Figure 5
. Input pro-
tection diodes are connected to the internal 5 volt power
supply rail and not to the output buffer supply rail. This
allows the input to withstand a maximum voltage of >5
volts, even when the I/O power pins connect to 3.3 volts.
Since both output transistors are N-channel devices, there
is no parasitic diode to be forward biased if the output is in
a 3-state condition and a 5 volt device is driving the
XC9500 I/O pin. Therefore, the device can operate on a bus
that includes both 3.3 volt and 5 volt devices.
XC9500 devices are TTL-compatible with 3.3 and 5 volt
logic as shown in
Figure 7
. The 5 volt TTL logic input
thresholds are VIH = 2.0 V and VIL = 0.8 V. XC9500 CPLDs
drive HIGH greater than 2.4 volts and LOW below 0.4 volts
at the rated output drive currents, with at least 400 mV
noise margin.
Figure 5: XC9500 I/O Architecture
Figure 6: Typical Mixed Voltage System
Can Be Driven By
0-3.3 V or 0-5 V
Output
Drivers
Input
Buffers
V
CCIO
(3.3 V)
V
CCINT
(5 V)
I/O Pin
V
CCINT
(5 V)
X3311
IN
OUT
XC9500
CPLD
V
CCINT
V
CCIO
5 V
5 V CMOS
5 V
or
or
0 V
3.3 V
GND
(b)
X5901
5 V TTL
3.6 V
0 V
3.3 V
3.3 V
0 V
3.3 V
3.3 V
0 V
IN
OUT
XC9500
CPLD
V
CCINT
V
CCIO
5 V
5 V CMOS
5 V
or
or
0 V
GND
(a)
5 V TTL
3.6 V
0 V
3.3 V
3.3 V
0 V
5 V TTL
~ 4 V
0 V
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| XC95108-10PCG84C | 制造商:Xilinx 功能描述:XLXXC95108-10PCG84C IC SYSTEM GATE |
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| XC95108-10PQ100C0586 | 制造商:Xilinx 功能描述: |
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