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參數(shù)資料
| 型號： | XC95108 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | In-System Programmable CPLD(在系統(tǒng)復(fù)雜可編程邏輯器件) |
| 中文描述： | 在系統(tǒng)可編程的CPLD（在系統(tǒng)復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 74K |
| 代理商： | XC95108 |
Designing with XC9500 CPLDs
2-22
XAPP073 January, 1998 (Version 1.3)
Automatic Software
The following design examples are created in ABEL. Typi-
cally, designers won’t designate specific function mapping
into XC9500 designs. However, designers occasionally like
to control how a solution is implemented, and in that case,
these methods may be of interest.
Boolean operators used by ABEL are
!
for invert,
#
for OR,
and
&
for AND. Combinatorial logic expressions are formed
with an equal sign, with operands and operators located on
the right hand side of the expression.
Flip-flops are formed by writing expressions for the specific
control pins of the flip-flop. The D-input is a special case,
represented by the compound symbol “:=”. Clock inputs are
determined by the syntax flip-flop_nameclk, and reset
inputs are designated by flip-flop_namerst.
An ABEL design file contains a header section including
optional documentation sections and mandatory declara-
tion of inputs, outputs, global signals, and any user pre-
ferred arrangement of functions.
Logic AND
The FastCONNECT switch matrix is capable of combining
signals with a wire-AND function. Signals entering the Fast-
CONNECT matrix are assigned to function block inputs,
and multiple signals, may form a wired-AND function, which
reduces the macrocell logic requirements. This feature
increases both the logic capacity and available signal
inputs to the Function Blocks.
Gates
The following expressions show the basic logic operations.
ABAR = !A;
AORB = A#B;
AANDB = A&B;
ANORB = !(A#B);
ANANDB = !(A&B);
AEXORB = A$B;
AEXNORB = A!$B;
Multiplexers and Decoders
Using the above methods, compound expressions are
formed to build logic functions. Using A0 to A3, B0 to B3,
and SEL (select) as inputs, a multiplexer is described as fol-
lows:
DAT0 = SEL&A0 # !SEL&B0;
DAT1 = SEL&A1 # !SEL&B1;
DAT2 = SEL&A2 # !SEL&B2;
DAT3 = SEL&A3 # !SEL&B3;
The approach extends to larger multiplexers. The previous
example uses one macrocell per data bit and leaves behind
two unused product terms in each macrocell. To take
advantage of four product terms per macrocell, the imple-
mentation expands as follows:
DAT0 = S1&S0&D0 # S1&!S0&C0 #
!S1&S0&B0 #!S1&!S0&A0;
DAT1 = S1&S0&D1 # S1&!S0&C1 #
!S1&S0&B1 #!S1&!S0&A1;
DAT2 = S1&S0&D2 # S1&!S0&C2 #
!S1&S0&B2 #!S1&!S0&A2;
DAT3 = S1&S0&D3 # S1&!S0&C3 #
!S1&S0&B3 #!S1&!S0&A3;
Very high speed decoders can be built in the macrocells to
form SRAM select signals, but do not use all of the macro-
cell product terms or the flip-flop in most cases. Decoders
are formed as follows:
DEC0 = !A3&!A2&!A1&!A0;
DEC1 = !A3&!A2&!A1&A0;
DEC2 = !A3&!A2&A1&!A0;
Registers
Simple registers are formed as follows:
A:= DATAINPUT;
A.CLK = CLOCK;
A.RST = RESET;
This describes a D-type flip-flop with its input tied to a sig-
nal named DATAINPUT, its clock tied to a signal called
CLOCK, and its reset input tied to a signal called RESET.
Shift Registers
Cascading registers results in a shift register as follows:
A:=DATAINPUT;
B:=A;
C:=B;
D:=C;
A.CLK = CLOCK;
B.CLK = CLOCK;
C.CLK = CLOCK;
D.CLK = CLOCK;
A.RST = RESET;
B.RST = RESET;
C.RST = RESET;
D.RST = RESET;
This shift register uses four macrocells. If the signals desig-
nated A,B,C,D are declared as outputs, they will appear
somewhere at the pins of an XC9500 device. If A,B,C, and
D are declared as nodes (internal points), the software
implements them within the macrocells.
Counters
Counters can be built in a number of ways. The most effi-
cient method is to have the macrocell flip-flops configured
as T-type flip-flops. The following equations form T-type flip-
flops; they add logic to load, hold, increment, and clear the
flip-flops. Note the compact vector notation:
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