參數(shù)資料
型號(hào): XC6VCX75T-1FFG484I
廠商: Xilinx Inc
文件頁數(shù): 45/52頁
文件大小: 0K
描述: IC FPGA VIRTEX 6 74K 484FFGBGA
產(chǎn)品培訓(xùn)模塊: Virtex-6 FPGA Overview
產(chǎn)品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex® 6 CXT
LAB/CLB數(shù): 5820
邏輯元件/單元數(shù): 74496
RAM 位總計(jì): 5750784
輸入/輸出數(shù): 240
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 484-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 484-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
5
GTX Transceivers in CXT Devices
CXT devices have between 8 to 16 gigabit transceiver circuits. Each GTX transceiver is a combined transmitter and receiver
capable of operating at a data rate between 480 Mb/s and 3.75 Gb/s. Lower data rates can be achieved using FPGA logic-
based oversampling. The transmitter and receiver are independent circuits that use separate PLLs to multiply the reference
frequency input by certain programmable numbers between 2 and 25, to become the bit-serial data clock. Each GTX
transceiver has a large number of user-definable features and parameters. All of these can be defined during device
configuration, and many can also be modified during operation.
Table 8: Available I/O Pin/Device/Package Combinations
Virtex-6
CXT Device
User I/O Pins
Virtex-6 CXT FPGA Package
FF484
FF784
FF1156
XC6VCX75T
Available User I/Os
240
360
Differential I/O Pairs
120
180
XC6VCX130T
Available User I/Os
240
400
600
Differential I/O Pairs
120
200
300
XC6VCX195T
Available User I/Os
400
600
Differential I/O Pairs
200
300
XC6VCX240T
Available User I/Os
400
600
Differential I/O Pairs
200
300
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