參數(shù)資料
型號： XC6VCX75T-1FFG484I
廠商： Xilinx Inc
文件頁數(shù)： 35/52頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX 6 74K 484FFGBGA
產(chǎn)品培訓模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標準包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 5820
邏輯元件/單元數(shù)： 74496
RAM 位總計： 5750784
輸入/輸出數(shù)： 240
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BBGA，F(xiàn)CBGA
供應商設備封裝： 484-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
40
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT}
{A, B} input to {ACOUT, BCOUT} output
0.65
0.75
ns
TDSPDO_{A, B}_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_MULT
{A, B} input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output using multiplier
5.24
6.03
ns
TDSPDO_D_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_MULT
D input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output using multiplier
4.94
5.68
ns
TDSPDO_{A, B}_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}
{A, B} input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output not using multiplier
2.19
2.52
ns
TDSPDO__{C, CARRYIN}_{PCOUT,
CARRYCASCOUT,MULTSIGNOUT}
{C, CARRYIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output
1.95
2.25
ns
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_{ACIN, BCIN}_{P, CARRYOUT}_MULT
{ACIN, BCIN} input to {P, CARRYOUT} output
using multiplier
4.97
5.72
ns
TDSPDO_{ACIN, BCIN}_{P, CARRYOUT
{ACIN, BCIN} input to {P, CARRYOUT} output
not using multiplier
1.92
2.21
ns
TDSPDO_{ACIN; BCIN}_{ACOUT; BCOUT}
{ACIN, BCIN} input to {ACOUT, BCOUT} output
0.49
0.57
ns
TDSPDO_{ACIN, BCIN}_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_MULT
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output
using multiplier
5.10
5.86
ns
TDSPDO_{ACIN, BCIN}_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output not
using multiplier
2.05
2.35
ns
TDSPDO_{PCIN, CARRYCASCIN, MULTSIGNIN}_
{P, CARRYOUT}
{PCIN, CARRYCASCIN, MULTSIGNIN} input to
{P, CARRYOUT} output
1.60
1.83
ns
TDSPDO_{PCIN, CARRYCASCIN, MULTSIGNIN}_ {PCOUT,
CARRYCASCOUT, MULTSIGNOUT}
{PCIN, CARRYCASCIN, MULTSIGNIN} input to
{PCOUT, CARRYCASCOUT, MULTSIGNOUT}
output
1.72
1.98
ns
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_{P, CARRYOUT}_PREG
CLK (PREG) to {P, CARRYOUT} output
0.50
0.57
ns
TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_PREG
CLK (PREG) to {CARRYCASCOUT, PCOUT,
MULTSIGNOUT} output
0.50
0.66
ns
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_{P, CARRYOUT}_MREG
CLK (MREG) to {P, CARRYOUT} output
2.30
2.65
ns
TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_MREG
CLK (MREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
2.43
2.79
ns
TDSPCKO_{P, CARRYOUT}_ADREG_MULT
CLK (ADREG) to {P, CARRYOUT} output
3.72
4.72
ns
TDSPCKO_{PCOUT, CARRYCASCOUT,
MULTSIGNOUT}_ADREG_MULT
CLK (ADREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
3.84
4.42
ns
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_{P, CARRYOUT}_{AREG, BREG}_MULT
CLK (AREG, BREG) to {P, CARRYOUT} output
using multiplier
5.36
6.16
ns
TDSPCKO_{P, CARRYOUT}_{AREG, BREG}
CLK (AREG, BREG) to {P, CARRYOUT} output
not using multiplier
2.27
2.61
ns
TDSPCKO_{P, CARRYOUT}_CREG
CLK (CREG) to {P, CARRYOUT} output
2.27
2.61
ns
TDSPCKO_{P, CARRYOUT}_DREG_MULT
CLK (DREG) to {P, CARRYOUT} output
5.25
6.04
ns
Table 51: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
Units
-2
-1
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