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參數(shù)資料
| 型號(hào)： | XC6VCX75T-1FFG484I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 44/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA VIRTEX 6 74K 484FFGBGA |
| 產(chǎn)品培訓(xùn)模塊： | Virtex-6 FPGA Overview |
| 產(chǎn)品變化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex® 6 CXT |
| LAB/CLB數(shù)： | 5820 |
| 邏輯元件/單元數(shù)： | 74496 |
| RAM 位總計(jì)： | 5750784 |
| 輸入/輸出數(shù)： | 240 |
| 電源電壓： | 0.95 V ~ 1.05 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 484-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 484-FCBGA |
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Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
49
Clock Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-6 CXT FPGA clock
transmitter and receiver data-valid windows.
Table 64: Duty Cycle Distortion and Clock-Tree Skew
Symbol
Description
Device
Speed Grade
Units
-2
-1
TDCD_CLK
Global Clock Tree Duty Cycle Distortion(1)
All
0.12
ns
TCKSKEW
Global Clock Tree Skew(2)
XC6VCX75T
0.18
ns
XC6VCX130T
0.29
ns
XC6VCX195T
0.31
ns
XC6VCX240T
0.31
ns
TDCD_BUFIO
I/O clock tree duty cycle distortion
All
0.08
ns
TBUFIOSKEW
I/O clock tree skew across one clock region
All
0.03
ns
TBUFIOSKEW2
I/O clock tree skew across three clock regions
All
0.22
ns
TDCD_BUFR
Regional clock tree duty cycle distortion
All
0.15
ns
Notes:
1.
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2.
The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
Table 65: Package Skew
Symbol
Description
Device
Package
Value
Units
TPKGSKEW
Package Skew(1)
XC6VCX75T
FF484
ps
FF784
ps
XC6VCX130T
FF484
95
ps
FF784
146
ps
FF1156
165
ps
XC6VCX195T
FF784
ps
FF1156
ps
XC6VCX240T
FF784
146
ps
FF1156
182
ps
Notes:
1.
These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time
from Pad to Ball (7.0 ps per mm).
2.
Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
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| XC6VCX75T-1FFG784C | 功能描述:IC FPGA VIRTEX 6 74K 784FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 CXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC6VCX75T-1FFG784I | 功能描述:IC FPGA VIRTEX 6 74K 784FFGBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 6 CXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC6VCX75T-2FF484C | 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 75K 484BGA |
| XC6VCX75T-2FF484I | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 74496 CELLS 40NM (CMOS) TECHNOLOGY - Trays 制造商:Xilinx 功能描述:IC FPGA 240 I/O 484FCBGA |
| XC6VCX75T-2FF784C | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 74496 CELLS 40NM (CMOS) TECHNOLOGY - Trays 制造商:Xilinx 功能描述:IC FPGA 360 I/O 784FCBGA |
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