參數(shù)資料
型號： XC6VCX75T-1FFG484I
廠商： Xilinx Inc
文件頁數(shù)： 22/52頁
文件大小： 0K
描述： IC FPGA VIRTEX 6 74K 484FFGBGA
產(chǎn)品培訓(xùn)模塊： Virtex-6 FPGA Overview
產(chǎn)品變化通告： Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝： 1
系列： Virtex® 6 CXT
LAB/CLB數(shù)： 5820
邏輯元件/單元數(shù)： 74496
RAM 位總計(jì)： 5750784
輸入/輸出數(shù)： 240
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 484-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 484-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
29
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 40 shows the test setup parameters used for measuring input delay.
DIFF_SSTL18_II_T_DCI
1.09
1.67
ns
DIFF_SSTL15
1.06
1.71
ns
DIFF_SSTL15_DCI
1.06
1.68
ns
DIFF_SSTL15_T_DCI
1.06
1.68
ns
Table 39: IOB 3-state ON Output Switching Characteristics (TIOTPHZ)
Symbol
Description
Speed Grade
Units
-2
-1
TIOTPHZ
T input to Pad high-impedance
0.99
ns
Table 38: IOB Switching Characteristics (Cont’d)
I/O Standard
TIOPI
TIOOP
TIOTP
Units
Speed Grade
-2
-1
-2
-1
-2
-1
Table 40: Input Delay Measurement Methodology
Description
I
/O Standard Attribute
VMEAS
(1,4,5)
VREF
(1,3,5)
LVCMOS, 2.5V
LVCMOS25
0
2.5
1.25
–
LVCMOS, 1.8V
LVCMOS18
0
1.8
0.9
–
LVCMOS, 1.5V
LVCMOS15
0
1.5
0.75
–
HSTL (High-Speed Transceiver Logic),
Class I & II
HSTL_I, HSTL_II
VREF –0.5
VREF +0.5
VREF
0.75
HSTL, Class III
HSTL_III
VREF –0.5
VREF +0.5
VREF
0.90
HSTL, Class I & II, 1.8V
HSTL_I_18, HSTL_II_18
VREF –0.5
VREF +0.5
VREF
0.90
HSTL, Class III 1.8V
HSTL_III_18
VREF –0.5
VREF +0.5
VREF
1.08
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL3_I, SSTL3_II
VREF –1.00
VREF +1.00
VREF
1.5
SSTL, Class I & II, 2.5V
SSTL2_I, SSTL2_II
VREF –0.75
VREF +0.75
VREF
1.25
SSTL, Class I & II, 1.8V
SSTL18_I, SSTL18_II
VREF –0.5
VREF +0.5
VREF
0.90
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS_25
1.2 – 0.125
1.2 + 0.125
–
LVDSEXT (LVDS Extended Mode), 2.5V
LVDSEXT_25
1.2 – 0.125
1.2 + 0.125
–
HT (HyperTransport), 2.5V
LDT_25
0.6 – 0.125
0.6 + 0.125
–
Notes:
1.
The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
2.
Input waveform switches between VLand VH.
3.
Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF
values listed are typical.
4.
Input voltage level from which measurement starts.
5.
This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 14.
6.
The value given is the differential output voltage.
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