參數(shù)資料
型號： XC4VSX35-11FFG668C
廠商： Xilinx Inc
文件頁數(shù)： 57/58頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX-4 35K 668-FCBGA
標準包裝： 1
系列： Virtex®-4 SX
LAB/CLB數(shù)： 3840
邏輯元件/單元數(shù)： 34560
RAM 位總計： 3538944
輸入/輸出數(shù)： 448
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 668-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 668-FCBGA
配用： HW-V4-ML402-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4
807-1005-ND - DAUGHTER CARD WITH VIRTEX-4
HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668
其它名稱： 122-1499
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
8
SelectIO DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for IOL and IOH are guaranteed over the recom-
mended operating conditions at the VOL and VOH test
points. Only selected standards are tested. These are cho-
sen to ensure that all standards meet their specifications.
The selected standards are tested at a minimum VCCO with
the respective VOL and VOH voltage levels shown. Other
standards are sample tested.
Table 7: SelectIO DC Input and Output Levels
IOSTANDARD
Attribute
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
LVTTL
–0.2
0.8
2.0
3.45
0.4
2.4
Note(3)
LVCMOS33,
LVDCI33
–0.2
0.8
2.0
3.45
0.4
VCCO –0.4
Note(3)
LVCMOS25,
LVDCI25
–0.3
0.7
1.7
VCCO +0.3
0.4
VCCO –0.4
Note(3)
LVCMOS18,
LVDCI18
–0.3
35% VCCO
65% VCCO
VCCO +0.3
0.4
VCCO –0.45
Note(4)
LVCMOS15,
LVDCI15
–0.3
35% VCCO
65% VCCO
VCCO +0.3
0.4
VCCO –0.45
Note(4)
PCI33_3(5)
–0.2
30% VCCO
50% VCCO
VCCO
10% VCCO
90% VCCO
1.5
–0.5
PCI66_3(5)
–0.2
30% VCCO
50% VCCO
VCCO
10% VCCO
90% VCCO
1.5
–0.5
PCI-X(5)
–0.2
35% VCCO
50% VCCO
VCCO
10% VCCO
90% VCCO
1.5
–0.5
GTLP
–0.3
VREF –0.1
VREF + 0.1
–
0.6
N/A
36
N/A
GTL
–0.3
VREF –0.05
VREF + 0.05
–
0.4
N/A
32
N/A
HSTL I(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO –0.4
8
–8
HSTL II(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO – 0.4
16
–16
HSTL III(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO – 0.4
24
–8
HSTL IV(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO – 0.4
48
–8
DIFF HSTL II(2)
–0.3
50%
VCCO –0.1
50%
VCCO +0.1
VCCO +0.3
0.4
VCCO –0.4
–
SSTL2 I
–0.3
VREF –0.15
VREF +0.15
VCCO +0.3 VTT –0.61
VTT + 0.61
8.1
–8.1
SSTL2 II
–0.3
VREF –0.15
VREF +0.15
VCCO +0.3 VTT –0.81
VTT + 0.81
16.2
–16.2
DIFF SSTL2 II
–0.3
50%
VCCO –0.15
50%
VCCO +0.15
VCCO +0.3
0.5
VCCO –0.5
–
SSTL18 I
–0.3
VREF – 0.125
VREF + 0.125
VCCO +0.3 VTT –0.47
VTT + 0.47
6.7
–6.7
SSTL18 II
–0.3
VREF – 0.125
VREF +0.125
VCCO +0.3 VTT –0.60
VTT + 0.60
13.4
–13.4
DIFF SSTL18 II
–0.3
50%
VCCO –0.125
50%
VCCO +0.125
VCCO +0.3
0.4
VCCO –0.4
–
Notes:
1.
Tested according to relevant specifications.
2.
Applies to both 1.5V and 1.8V HSTL.
3.
LVCMOS using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4.
LVCMOS using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5.
For more information on PCI33_3, PCI66_3, and PCI-X, refer to the Virtex-4 FPGA User Guide, SelectIO Resources, Chapter 6.
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