參數(shù)資料
型號(hào)： XC4VSX35-11FFG668C
廠商： Xilinx Inc
文件頁數(shù)： 26/58頁
文件大小： 0K
描述： IC FPGA VIRTEX-4 35K 668-FCBGA
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-4 SX
LAB/CLB數(shù)： 3840
邏輯元件/單元數(shù)： 34560
RAM 位總計(jì)： 3538944
輸入/輸出數(shù)： 448
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 668-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 668-FCBGA
配用： HW-V4-ML402-UNI-G-ND - EVALUATION PLATFORM VIRTEX-4
807-1005-ND - DAUGHTER CARD WITH VIRTEX-4
HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668
其它名稱： 122-1499
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
32
CLB Distributed RAM Switching Characteristics (SLICEM Only)
)
CLB Shift Register Switching Characteristics (SLICEM Only)
)
Table 38: CLB Distributed RAM Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
XC4VFX(2)
XC4VLX/SX
ALL DEVICES
Sequential Delays
TSHCKO
Clock CLK to X outputs (WE active)(3)
1.61
1.58
1.77
2.08
ns, Max
TSHCKOF5
Clock CLK to F5 output (WE active)
1.53
1.50
1.69
1.98
ns, Max
Setup and Hold Times Before/After Clock CLK
TDS / TDH
BX/BY data inputs (DI)
1.26
–0.90
1.23
–0.88
1.46
–0.88
1.80
–0.88
ns, Min
TAS / TAH
F/G address inputs
0.88
–0.37
0.86
–0.37
0.97
–0.34
1.13
–0.29
ns, Min
TWS / TWH
WE input (SR)
1.10
–0.48
1.08
–0.47
1.21
–0.47
1.42
–0.47
ns, Min
Clock CLK
TWPH
Minimum Pulse Width, High
0.53
0.52
0.59
0.69
ns, Min
TWPL
Minimum Pulse Width, Low
0.55
0.54
0.60
0.70
ns, Min
TWC
Minimum clock period to meet address write cycle time
0.76
0.74
0.84
0.98
ns, Min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2.
The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent
XC4VLX/SX -12 column.
3.
TSHCKO also represents the CLK to XMUX output. Refer to TRCE report for the CLK to XMUX path.
Table 39: CLB Shift Register Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
XC4VFX(2)
XC4VLX/SX
XC4VFX(3)
XC4VLX/SX
ALL
Sequential Delays
TREG
Clock CLK to X/Y outputs
2.12
2.08
2.19
2.57
ns, Max
TREGXB
Clock CLK to XB output via MC15 LUT output
1.83
1.73
1.90
1.84
2.16
ns, Max
TREGYB
Clock CLK to YB output via MC15 LUT output
1.84
1.74
1.92
1.85
2.17
ns, Max
TCKSH
Clock CLK to Shiftout
1.70
1.60
1.76
1.70
1.99
ns, Max
TREGF5
Clock CLK to F5 output
2.05
2.01
2.11
2.47
ns, Max
Setup and Hold Times Before/After Clock CLK
TWS / TWH
WE input (SR)
0.87
–0.76
0.85
–0.76
0.96
–0.70
0.96
–0.70
1.12
–0.62
ns, Min
TDS / TDH
BX/BY data inputs (DI)
1.28
–1.12
1.25
–1.11
1.45
–1.11
1.45
–1.11
1.75
–1.11
ns, Min
Clock CLK
TWPH
Minimum Pulse Width, High
0.53
0.52
0.59
0.69
ns, Min
TWPL
Minimum Pulse Width, Low
0.55
0.54
0.60
0.70
ns, Min
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2.
The values in this column apply to all XC4VFX -12 parts except XC4VFX12 -12. For XC4VFX12 -12 values, use the values in the adjacent
XC4VLX/SX -12 column.
3.
The values in this column apply to all XC4VFX -11 parts.
相關(guān)PDF資料
PDF描述
XC5VLX50T-1FF1136C IC FPGA VIRTEX-5 50K 1136FBGA
XC5VLX50T-1FFG1136C IC FPGA VIRTEX-5 50K 1136FBGA
AT24C02C-XHM-T IC EEPROM 2KBIT 1MHZ 8TSSOP
XC2V1500-4FF896I IC FPGA VIRTEX-II 896FCBGA
AT24C02C-STUM-T IC EEPROM 2KBIT 1MHZ SOT23-5
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4VSX35-11FFG668I 功能描述:IC FPGA VIRTEX-4 SX 35K 668FCBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-4 SX 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC4VSX35-12FFG668C 功能描述:IC FPGA VIRTEX-4 SX 35K 668FCBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Virtex®-4 SX 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC4VSX35-9FF668I 制造商:Xilinx 功能描述:
XC4VSX55 制造商:XILINX 制造商全稱:XILINX 功能描述:DC and Switching Characteristics
XC4VSX55-10FF1148C 制造商:Xilinx 功能描述:FPGA VIRTEX-4 55296 CELLS 90NM 1.2V 1148FCBGA - Trays
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*