參數(shù)資料
型號： XC4VLX60-10FFG668C
廠商： Xilinx Inc
文件頁數(shù)： 9/58頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX-4 60K 668-FCBGA
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-4 LX
LAB/CLB數(shù)： 6656
邏輯元件/單元數(shù)： 59904
RAM 位總計： 2949120
輸入/輸出數(shù)： 448
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 668-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 668-FCBGA
配用： HW-AFX-FF668-400-ND - BOARD DEV VIRTEX 4 FF668
其它名稱： 122-1494
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
17
Table 25: RocketIO Receiver Switching Characteristics
Description
Symbol
Conditions
Min
Typ
Max
Units
Serial data rate, -10
FGRX
0.622
3.125
Gb/s
Serial data rate, -11
FGRX
0.622
6.5
Gb/s
XAUI Receive Jitter Tolerance (8B/10B CJPAT) (2)
Rate (Gb/s) Mode(3)
Frequency
Receive Deterministic Jitter Tolerance
TDJTOL
3.125
ACDR
0.37
UI(1)
Receive Total Jitter Tolerance
TTJTOL(6)
3.125
ACDR
0.65
Receive Sinusoidal Jitter Tolerance
TSJTOL(7)
3.125
ACDR
f = 22.1 kHz
8.5
3.125
ACDR
f = 1.875 MHz
0.10
3.125
ACDR
f = 20 MHz
0.10
General Receive Jitter Tolerance
Rate (Gb/s)
Pattern
Receive deterministic jitter tolerance
TDJTOL(2,4)
6.5(5)
ACDR
PRBS7
0.65
UI(1)
5.0(5)
ACDR
PRBS7
0.65
4.25(5)
ACDR
PRBS7
0.65
3.125
ACDR
PRBS7
0.60
2.5
ACDR
PRBS7
0.55
1.25
ACDR
PRBS7
0.50
1.25
DCDR
PRBS7
0.50
1.25
DCDR
PRBS31
0.40
0.622
DCDR
PRBS31
0.40
Sinusoidal jitter tolerance
TSJTOL
6.5(9)
ACDR
PRBS7
0.65
5.0(9)
ACDR
PRBS7
0.65
4.25(9)
ACDR
PRBS7
0.65
3.125(8)
ACDR
PRBS7
0.50
2.5(8)
ACDR
PRBS7
0.50
1.25(8)
ACDR
PRBS7
0.50
1.25(8)
DCDR
PRBS7
0.55
1.25(8)
DCDR
PRBS31
0.35
DCDR
PRBS31
0.55
RXUSRCLK frequency
TRX
For slower speed grades = MaxDataRate/32
250
MHz
RXUSRCLK2 frequency
TRX2
250
MHz
RXUSRCLK duty cycle
TRXDC
40
60
%
RXUSRCLK2 duty cycle
TRX2DC
40
60
%
Differential input skew
TISKEW
20
ps
Differential receive input sensitivity(2)
VEYE
110
mV
On-chip AC coupling corner frequency
Signal detect response time
RXSIGDETResponsetime
30
ns
Input capacitance at the Die
CDIE
fF
Excess capacitance at the solder ball
CBALL
fF
Notes:
1.
UI = Unit Interval
2.
Using receiver equalization setting of 111 (14 dB).
3.
ACDR = Analog CDR and DCDR = Digital CDR.
4.
Deterministic jitter (DJ) is composed of 75% ISI + 25% high frequency
sinusoidal jitter (SJ).
5.
Deterministic Jitter (DJ) composed of ISI + 0.10 UI of high frequency SJ +
0.15 UI of RJ.
6.
Sum of DJ, random jitter (RJ) of at least 0.55 UI, and sinusoidal jitter
as defined by mask in IEEE Std 802.3ae-2002, Figure 47-5.
7.
SJ in addition to 0.55 UI of DJ +RJ.
8.
Jitter frequency = 5 MHz.
9.
Jitter frequency = 10 MHz.
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