- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374986 > XC4004A (Xilinx, Inc.) Logic Cell Array Family PDF資料下載
參數(shù)資料
| 型號(hào)： | XC4004A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 97K |
| 代理商： | XC4004A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
2-75
P
Speed Grade
-6
-5
-4
Description
Symbol
Device
Units
Global Clock to Output (fast)
T
ICKOF
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
14.9
15.1
15.3
15.5
19.9
20.1
20.3
20.5
2.6
2.4
2.2
2.0
4.9
5.1
5.3
5.5
21.8
21.5
21.2
21.0
0
0
0
0
12.2
12.5
12.8
13.0
15.2
15.5
15.8
16.0
2.3
2.0
1.7
1.5
3.7
4.0
4.3
4.5
18.8
18.5
18.2
18.0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11.6
(Max)
12.0
Global Clock to Output (slew limited)
T
ICKO
14.6
(Max)
15.0
Input Set-up Time, using IFF (no delay)
T
PSUF
1.6
(Min)
1.2
Input Hold time, using IFF (no delay)
T
PHF
4.0
(Min)
4.5
Input Set-up Time, using IFF (with delay)
T
PSU
12.0
(Min)
12.0
Input Hold Time, using IFF (with delay)
T
PH
(Min)
0
Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly. and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a discrepancy
between these two methods, the directly tested values listed below should be used, and the derived values should be ignored.
IFF
Input
Set-Up
&
Hold
Time
OFF
Global Clock-to-Output Delay
X3192
T
PG
Timing is measured at pin threshold, with 50 pF external
capacitive loads (incl. test fixture). When testing fast out-
puts, only one output switches. When testing slew-rate
limited outputs, half the number of outputs on one side of the
device are switching. These parameter values are tested
and guaranteed for worst-case conditions of supply voltage
and temperature, and also with the most unfavorable clock
polarity choice.
PRELIMINARY
PRELIMINARY
See page 2-76
Pad to I1, I2
via transparent
latch, with delay
XC4003A 17.6 ns
T
PDLI
for -4 Speed Grade
Input set-up time
pad to clock (IK)
with delay
XC4003A 15.6 ns
T
PICKD
for -4 Speed Grade
X6091
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC4005A | Logic Cell Array Family |
| XC4005A-5PQ160C | Logic Cell Array Family |
| XC4005-36XL | XC4000XL Electrical Specifications |
| XC4010E | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4010E-4PG191C | XC4000E and XC4000X Series Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4004A-5PC84C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC4004A-5PG120C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC4004A-5PQ160C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC4004A-5TQ144C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC4004A-6PC84C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。