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參數(shù)資料
| 型號： | XC4004A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 97K |
| 代理商： | XC4004A |
2-81
XC4002A Pinouts
*
Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 199 = BSCANT.UPD
Indicates unconnected package pins.
Pin
Description
Bound
Scan
Pin
Description
Bound
Scan
Pin
Description
Bound
Scan
PC 84 PQ100 VQ100 PG120
PC 84 PQ100 VQ100 PG120
PC 84 PQ100 VQ100 PG120
VCC
2
92
89
G3
–
I/O
28
23
20
C9
92
–
–
–
–
L9
–
I/O (A8)
3
93
90
G1
26
SGCK2 (I/O)
29
24
21
A12
95
I/O (D6)
58
58
55
M10
157
I/O (A9)
4
94
91
F1
29
O (M1)
30
25
22
B11
98
I/O
–
59
56
N11
160
–
–
95
*
*
92
*
*
E1
*
*
–
GND
31
26
23
C10
–
I/O (D5)
59
60
57
M9
163
–
–
96
93
F2
–
I (M0)
32
27
24
C11
101
I/O (
CSO
)
60
61
58
N10
166
I/O (A10)
5
97
94
F3
32
VCC
33
28
25
D11
–
–
–
62
*
*
59
*
*
L8
*
*
–
I/O (A11)
6
98
95
D1
35
I (M2)
34
29
26
B12
102
–
–
63
60
N9
–
–
–
–
–
E2
*
–
PGCK2 (I/O)
35
30
27
C12
103
I/O (D4)
61
64
61
M8
169
I/O (A12)
7
99
96
C1
38
I/O (HDC)
36
31
28
A13
106
I/O
62
65
62
N8
172
I/O (A13)
8
100
97
D2
41
–
–
–
–
B13
*
*
–
VCC
63
66
63
M7
–
–
–
–
–
E3
*
*
–
–
–
–
–
E11
–
GND
64
67
64
L7
–
–
–
–
–
B1
–
I/O
–
32
29
D12
109
I/O (D3)
65
68
65
N7
175
I/O (A14)
9
1
98
C2
44
I/O (
LDC
)
37
33
30
C13
112
I/O (
RS
)
66
69
66
N6
178
SGCK1 (A15, I/O)
10
2
99
D3
47
I/O
38
34
31
E12
115
–
–
70
*
67
*
N5
*
*
–
VCC
11
3
100
C3
–
I/O
39
35
32
D13
118
–
–
–
–
M6
–
GND
12
4
1
C4
–
–
–
36
*
*
33
*
*
F11
*
*
–
I/O (D2)
67
71
68
L6
181
PGCK1 (A16, I/O)
13
5
2
B2
50
–
–
37
34
E13
–
I/O
68
72
69
N4
184
I/O (A17)
14
6
3
B3
53
I/O
40
38
35
F12
121
I/O (D1)
69
73
70
M5
187
–
–
–
–
A1
*
*
–
I/O (
ERR
,
INIT
)
41
39
36
F13
124
I/O (RCLK-BUSY/RDY)
70
74
71
N3
190
–
–
–
–
A2
–
VCC
42
40
37
G12
–
–
–
–
–
M4
*
*
–
I/O (TDI)
15
7
4
C5
56
GND
43
41
38
G11
–
–
–
–
–
L5
–
I/O (TCK)
16
8
5
B4
59
I/O
44
42
39
G13
127
I/O (D0, DIN)
71
75
72
N2
193
–
–
–
–
A3
*
–
I/O
45
43
40
H13
130
SGCK4 (DOUT, I/O)
72
76
73
M3
196
I/O (TMS)
17
9
6
B5
62
–
–
44
*
*
41
*
*
J13
*
*
–
CCLK
73
77
74
L4
–
I/O
18
10
7
A4
65
–
–
45
42
H12
–
VCC
74
78
75
L3
–
–
–
–
–
C6
*
*
–
I/O
46
46
43
H11
133
O (TDO)
75
79
76
M2
–
–
–
11
*
8
*
A5
–
I/O
47
47
44
K13
136
GND
76
80
77
K3
–
I/O
19
12
9
B6
68
I/O
48
48
45
J12
139
I/O (A0,
WS
)
77
81
78
L2
2
I/O
20
13
10
A6
71
I/O
49
49
46
L13
142
PGCK4 (I/O,A1)
78
82
79
N1
5
GND
21
14
11
B7
–
–
–
–
–
K12
*
*
–
–
–
–
–
M1
*
*
–
VCC
22
15
12
C7
–
–
–
–
–
J11
–
–
–
–
–
J3
–
I/O
23
16
13
A7
74
I/O
50
50
47
M13
145
I/O (CS1, A2)
79
83
80
K2
8
I/O
24
17
14
A8
77
SGCK3 (I/O)
51
51
48
L12
148
I/O (A3)
80
84
81
L1
11
–
–
18
*
15
*
A9
*
*
–
GND
52
52
49
K11
–
I/O (A4)
81
85
82
J2
14
–
–
–
–
B8
–
DONE
53
53
50
L11
–
I/O (A5)
82
86
83
K1
17
I/O
25
19
16
C8
80
VCC
54
54
51
L10
–
–
–
87
*
*
84
*
*
H3
*
*
–
I/O
26
20
17
A10
83
PROG
55
55
52
M12
–
–
–
88
85
J1
–
I/O
27
21
18
B9
86
I/O (D7)
56
56
53
M11
151
I/O (A6)
83
89
86
H2
20
I/O
–
22
19
A11
89
PGCK3 (I/O)
57
57
54
N13
154
I/O (A7)
84
90
87
H1
23
–
–
–
–
B10
*
–
–
–
–
–
N12
*
–
GND
1
91
88
G2
–
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| XC4005A | Logic Cell Array Family |
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