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參數(shù)資料
| 型號： | XC4004A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 97K |
| 代理商： | XC4004A |
2-73
P
Speed Grade
-6
-5
-4
Description
Symbol
Device
Max
Max
Max
Units
Global Signal Distribution
From pad through
primary
buffer, to any clock k
T
PG
XC4002A
XC4003A
XC4004A
XC4005A
7.7
7.8
7.9
8.0
5.7
5.8
5.9
6.0
ns
ns
ns
ns
5.1
5.5
From pad through
secondary
buffer, to any clock k
T
SG
XC4002A
XC4003A
XC4004A
XC4005A
8.7
8.8
8.9
9.0
6.7
6.8
6.9
7.0
ns
ns
ns
ns
6.3
P
9.0
Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, there derived from benchmark timing patterns. The following
guidelines relflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date
timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
-4
Description
Symbol
Device
Max
Max
Max
Units
Full length, both pull-ups,
inputs from IOB I-pins
T
WAF
XC4002A
XC4003A
XC4004A
XC4005A
8.5
9.0
9.5
10.0
7.5
8.0
8.5
9.0
ns
ns
ns
ns
5.0
6.0
Full length, both pull-ups
inputs from internal logic
T
WAFL
XC4002A
XC4003A
XC4004A
XC4005A
11.5
12.0
12.5
13.0
10.5
11.0
11.5
12.0
ns
ns
ns
ns
7.0
8.0
Half length, one pull-up
inputs from IOB I-pins
T
WAO
XC4002A
XC4003A
XC4004A
XC4005A
8.5
9.0
9.5
10.0
7.5
8.0
8.5
9.0
ns
ns
ns
ns
6.0
7.0
Half length, one pull-up
inputs from internal logic
T
WAOL
XC4002A
XC4003A
XC4004A
XC4005A
11.5
12.0
12.5
13.0
10.5
11.0
11.5
12.0
ns
ns
ns
ns
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (T
PID
)
and output delay (one of 4 modes), as listed on page 2-70.
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC4005A | Logic Cell Array Family |
| XC4005A-5PQ160C | Logic Cell Array Family |
| XC4005-36XL | XC4000XL Electrical Specifications |
| XC4010E | XC4000E and XC4000X Series Field Programmable Gate Arrays |
| XC4010E-4PG191C | XC4000E and XC4000X Series Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC4004A-5PC84C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC4004A-5PG120C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC4004A-5PQ160C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC4004A-5TQ144C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC4004A-6PC84C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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