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參數(shù)資料
| 型號： | XC4004A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Family |
| 中文描述： | 邏輯單元陣列系列 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 97K |
| 代理商： | XC4004A |
XC4000A Logic Cell Array Family
2-74
P
Speed Grade
-6
-5
-4
Description
Symbol
Device
Max
Max
Max
Units
TBUF
driving a Horizontal Longline (L.L.)
I going High or Low to L.L. going High or Low,
while T is Low, i.e. buffer is constantly active
T
IO1
XC4002A
XC4003A
XC4004A
XC4005A
8.2
8.8
9.4
10.0
6.0
6.2
6.6
7.0
ns
ns
ns
ns
4.4
5.5
I
going Low to L.L. going from resistive pull-up
High to active Low, (TBUF configured as open drain)
T
IO2
XC4002A
XC4003A
XC4004A
XC4005A
8.7
9.3
9.9
10.5
6.5
6.7
7.1
7.5
ns
ns
ns
ns
5.0
6.0
T
going Low to L.L. going from resistive pull-up
or floating High to active Low, (TUBF configured
as open drain)
T
ON
XC4002A
XC4003A
XC4004A
XC4005A
10.1
10.7
11.4
12.0
8.4
9.0
9.5
10.0
ns
ns
ns
ns
7.2
8.0
T
going High to TBUF going inactive, not driving L.L.
T
OFF
All devices
3.0
2.0
1.8
ns
T
going High to L.L. going from Low to High,
pulled up by a single resistor
T
PUS
XC4002A
XC4003A
XC4004A
XC4005A
23.0
24.0
25.0
26.0
19.0
20.0
21.0
22.0
ns
ns
ns
ns
14.0
16.0
T
going High to L.L. going from Low to High,
pulled up by two resistors
T
PUF
XC4002A
XC4003A
XC4004A
XC4005A
10.5
11.0
11.5
12.0
8.5
9.0
9.5
10.0
ns
ns
ns
ns
7.0
8.0
Horizontal Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
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