參數(shù)資料
型號： XC3S400AN-4FG400I
廠商： Xilinx Inc
文件頁數(shù)： 75/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 3AN 400FBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-3AN
LAB/CLB數(shù)： 896
邏輯元件/單元數(shù)： 8064
RAM 位總計(jì)： 368640
輸入/輸出數(shù)： 311
門數(shù)： 400000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 400-BGA
供應(yīng)商設(shè)備封裝： 400-FBGA（21x21）
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
55
Table 42: Switching Characteristics for the DFS
Symbol
Description
Device
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_FX
Frequency for the CLKFX and CLKFX180 outputs
All
5
350
5
320
MHz
Output Clock Jitter (2)(3)
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and
CLKFX180 outputs.
CLKIN
20 MHz
All
Typ
Max
Typ
Max
Use the Spartan-3A Jitter
Calculator:
ps
CLKIN
> 20 MHz
±[1% of
CLKFX
period
+ 100]
±[1% of
CLKFX
period
+ 200]
±[1% of
CLKFX
period
+ 100]
±[1% of
CLKFX
period
+ 200]
ps
Duty Cycle(4)(5)
CLKOUT_DUTY_CYCLE_FX
Duty cycle precision for the CLKFX and CLKFX180
outputs, including the BUFGMUX and clock tree
duty-cycle distortion
All
–±[1% of
CLKFX
period
+ 350]
–±[1% of
CLKFX
period
+ 350]
ps
Phase Alignment(5)
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX
output and the DLL CLK0 output when
both the DFS and DLL are used
All
–±200
ps
CLKOUT_PHASE_FX180 Phase offset between the DFS
CLKFX180 output and the DLL CLK0
output when both the DFS and DLL
are used
All
–±[1% of
CLKFX
period
+ 200]
–±[1% of
CLKFX
period
+ 200]
ps
Lock Time
LOCK_FX(2)
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output. The
DFS asserts LOCKED when the
CLKFX and CLKFX180 signals are
valid. If using both the DLL and the
DFS, use the longer locking time.
5 MHz < FCLKIN
< 15 MHz
All
–5
ms
FCLKIN >
15 MHz
–450
–
450
s
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 10 and Table 41.
2.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
3.
Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an XC3S1400A FPGA.
Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching
activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application.
4.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
5.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a
maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
相關(guān)PDF資料
PDF描述
XC3SD1800A-4CSG484LI IC FPGA SPARTAN 3 DSP 484CSGBGA
XC3SD3400A-4FGG676I SPARTAN-3ADSP FPGA 3400K 676FBGA
XC4036XLA-09HQ240C IC FPGA C 2.5V 288 I/O 240HQFP
XC4062XL-09HQ240C IC FPGA C-TEMP 3.3V 240-HQFP
XC4085XL-3BG560I IC FPGA I-TEMP 3.3V 3SPD 560MBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3S400AN-4FG400I4100 制造商:Xilinx 功能描述:
XC3S400AN-4FGG400C 功能描述:IC SPARTAN-3AN FPGA 400K 400FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
XC3S400AN-4FGG400CES 制造商:Xilinx 功能描述:
XC3S400AN-4FGG400I 功能描述:IC FPGA SPARTAN-3A 400K 400-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27）
XC3S400AN-4FT256C 制造商:Xilinx 功能描述:SPARTAN3AN - Trays 制造商:Xilinx 功能描述:IC FPGA SPARTAN-3AN 400K 256BGA 制造商:Xilinx 功能描述:IC FPGA 195 I/O 256FTBGA
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*