- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4276 > XC3S400-5FGG320C (Xilinx Inc)SPARTAN-3A FPGA 400K 320-FBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | XC3S400-5FGG320C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 19/272頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 400K 320-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 896 |
| 邏輯元件/單元數(shù)： | 8064 |
| RAM 位總計(jì)： | 294912 |
| 輸入/輸出數(shù)： | 221 |
| 門數(shù)： | 400000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 320-BGA |
| 供應(yīng)商設(shè)備封裝： | 320-FBGA（19x19） |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)當(dāng)前第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)
Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013
Product Specification
115
JTAG Configuration Mode
In the JTAG configuration mode all dual-purpose configuration pins are unused and behave exactly like user-I/O pins, as
Dual-Purpose Pin I/O Standard During Configuration
During configuration, the dual-purpose pins default to CMOS input and output levels for the associated VCCO voltage
supply pins. For example, in the Parallel configuration modes, both VCCO_4 and VCCO_5 are required. If connected to
+2.5V, then the associated pins conform to the LVCMOS25 I/O standard. If connected to +3.3V, then the pins drive LVCMOS
output levels and accept either LVTTL or LVCMOS input levels.
Dual-Purpose Pin Behavior After Configuration
After the configuration process completes, these pins, if they were borrowed during configuration, become user-I/O pins
available to the application. If a dual-purpose configuration pin is not used during the configuration process—i.e., the parallel
configuration pins when using serial mode—then the pin behaves exactly like a general-purpose I/O. See I/O Type:
DCI: User I/O or Digitally Controlled Impedance Resistor Reference Input
These pins are individual user-I/O pins unless one of the I/O standards used in the bank requires the Digitally Controlled
Impedance (DCI) feature. If DCI is used, then 1% precision resistors connected to the VRP_# and VRN_# pins match the
impedance on the input or output buffers of the I/O standards that use DCI within the bank. The ‘#’ character in the pin name
indicates the associated I/O bank and is an integer, 0 through 7.
There are two DCI pins per I/O bank, except in the CP132 and TQ144 packages, which do not have any DCI inputs for
Bank 5.
VRP and VRN Impedance Resistor Reference Inputs
The 1% precision impedance-matching resistor attached to the VRP_# pin controls the pull-up impedance of PMOS
transistor in the input or output buffer. Consequently, the VRP_# pin must connect to ground. The ‘P’ character in “VRP”
indicates that this pin controls the I/O buffer’s PMOS transistor impedance. The VRP_# pin is used for both single and split
termination.
BUSY
Output
Configuration Data Rate Control for Parallel Mode:
In the Slave and Master Parallel modes, BUSY throttles the rate at which configuration data is loaded.
BUSY is only necessary if CCLK operates at greater than 50 MHz. Ignore BUSY for frequencies of 50
MHz and below.
When BUSY is Low, the FPGA accepts the next configuration data byte on the next rising CCLK edge for
which CS_B and RDWR_B are Low. When BUSY is High, the FPGA ignores the next configuration data
byte. The next configuration data value must be held or reloaded until the next rising CCLK edge when
BUSY is Low. When CS_B is High, BUSY is in a high impedance state.
This signal is located in Bank 4 and its output voltage is determined by VCCO_4. The BitGen option
Persist permits this pin to retain its configuration function in the User mode.
INIT_B
Bidirectional
(open-drain)
Initializing Configuration Memory/Configuration Error (active-Low):
See description under Serial Configuration Modes, page 112.
Table 72: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes (Cont’d)
Pin Name
Direction
Description
BUSY
Function
0
The FPGA is ready to accept the next configuration data byte.
1
The FPGA is busy processing the current configuration data byte and is not
ready to accept the next byte.
Hi-Z
If CS_B is High, then BUSY is high impedance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 93AA86BT-I/MS | IC EEPROM 16KBIT 1024X16 8-MSOP |
| 93AA86B-I/ST | IC EEPROM 16KBIT 1024X16 8-TSSOP |
| AMM31DRSI | CONN EDGECARD 62POS DIP .156 SLD |
| FSM28DSEN | CONN EDGECARD 56POS .156 EYELET |
| FSM28DSEH | CONN EDGECARD 56POS .156 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3S400-5FGG456C | 功能描述:SPARTAN-3A FPGA 400K 456-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC3S400-5FT256C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 400K GATES 8064 CELLS 725MHZ 1.2V 256FTBGA - Trays |
| XC3S400-5FT256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3 FPGA Family : Complete Data Sheet |
| XC3S400-5FTG256C | 功能描述:SPARTAN-3A FPGA 400K 256-FTBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-3 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC3S400-5PQ208C | 制造商:Xilinx 功能描述:FPGA SPARTAN-3 400K GATES 8064 CELLS 725MHZ 1.2V 208PQFP - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。