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參數(shù)資料
| 型號(hào)： | XC3S1500-4FGG676I |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 23/272頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | SPARTAN-3A FPGA 1.5M STD 676FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Extended Spartan 3A FPGA Family |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | Spartan®-3 |
| LAB/CLB數(shù)： | 3328 |
| 邏輯元件/單元數(shù)： | 29952 |
| RAM 位總計(jì)： | 589824 |
| 輸入/輸出數(shù)： | 487 |
| 門(mén)數(shù)： | 1500000 |
| 電源電壓： | 1.14 V ~ 1.26 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
| 配用： | NANO-SPARTAN-ND - KIT NANOBOARD AND SPARTAN3 DC 807-1001-ND - DAUGHTER CARD XILINX SPARTAN 3 |
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Spartan-3 FPGA Family: Pinout Descriptions
DS099 (v3.1) June 27, 2013
Product Specification
119
HSWAP_EN: Disable Pull-up Resistors During Configuration
As shown in Table 76, a Low on this asynchronous pin enables pull-up resistors on all user I/Os not actively involved in the
configuration process, although only until device configuration completes. A High disables the pull-up resistors during
configuration, which is the desired state for some applications.
The dedicated configuration CONFIG pins (CCLK, DONE, PROG_B, HSWAP_EN, M2, M1, M0), the JTAG pins (TDI, TMS,
TCK, TDO) and the INIT_B always have active pull-up resistors during configuration, regardless of the value on
HSWAP_EN.
After configuration, HSWAP_EN becomes a "don’t care" input and any pull-up resistors previously enabled by HSWAP_EN
are disabled. If a user I/O in the application requires a pull-up resistor after configuration, place a PULLUP primitive on the
associated I/O pin or, for some pins, set the associated bitstream generator option.
The Bitstream generator option HswapenPin determines whether a pull-up resistor to VCCAUX, a pull-down resistor, or no
resistor is present on HSWAP_EN after configuration.
JTAG: Dedicated JTAG Port Pins
These pins are dedicated connections to the four-wire IEEE 1532/IEEE 1149.1 JTAG port, shown in Figure 43 and
described in Table 77. The JTAG port is used for boundary-scan testing, device configuration, application debugging, and
possibly an additional serial port for the application. These pins are dedicated and are not available as user-I/O pins. Every
package has four dedicated JTAG pins and these pins are powered by the +2.5V VCCAUX supply.
For additional information on JTAG configuration, see Boundary-Scan (JTAG) Mode, page 50.
Table 76: HSWAP_EN Encoding
HSWAP_EN
Function
During Configuration
0
Enable pull-up resistors on all pins not actively involved in the configuration process. Pull-ups are only active until
configuration completes. See Table 79.
1
No pull-up resistors during configuration.
After Configuration, User Mode
X
This pin has no function except during device configuration.
Notes:
1.
X = don’t care, either 0 or 1.
Table 77: JTAG Pin Descriptions
Pin Name
Direction
Description
Bitstream Generation Option
TCK
Input
Test Clock: The TCK clock signal synchronizes all boundary
scan operations on its rising edge.
The BitGen option TckPin determines
whether a pull-up resistor, pull-down
resistor or no resistor is present.
TDI
Input
Test Data Input: TDI is the serial data input for all JTAG
instruction and data registers. This input is sampled on the
rising edge of TCK.
The BitGen option TdiPin determines
whether a pull-up resistor, pull-down
resistor or no resistor is present.
TMS
Input
Test Mode Select: The TMS input controls the sequence of
states through which the JTAG TAP state machine passes.
This input is sampled on the rising edge of TCK.
The BitGen option TmsPin determines
whether a pull-up resistor, pull-down
resistor or no resistor is present.
TDO
Output
Test Data Output: The TDO pin is the data output for all JTAG
instruction and data registers. This output is sampled on the
rising edge of TCK. The TDO output is an active totem-pole
driver and is not like the open-collector TDO output on
Virtex-II Pro FPGAs.
The BitGen option TdoPin determines
whether a pull-up resistor, pull-down
resistor or no resistor is present.
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