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參數(shù)資料
| 型號(hào)： | XC3195A-09PQ160C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 38/76頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA 7500 GATE 160-PQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 484 |
| RAM 位總計(jì)： | 94984 |
| 輸入/輸出數(shù)： | 138 |
| 門數(shù)： | 7500 |
| 電源電壓： | 4.25 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 其它名稱： | Q1428091 |
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R
November 9, 1998 (Version 3.1)
7-45
XC3000 Series Field Programmable Gate Arrays
7
XC3000A IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes:
1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. TPID, TPTG, and TPICK are 3 ns higher for XTL2 when the pin is configured as a user input.
Speed Grade
-7
-6
Description
Symbol
Min
Max
Min
Max
Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
3
4
TPID
TPTG
TIKRI
4.0
15.0
3.0
14.0
2.5
ns
Set-up Time (Input)
Pad to Clock (IK) set-up time
1
TPICK
14.0
12.0
ns
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (O) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z
(fast)
same
(slew-rate limited)
3-state to Pad active and valid
(fast)
same
(slew -rate limited)
7
10
9
8
TOKPO
TOPF
TOPS
TTSHZ
TTSON
8.0
18.0
6.0
16.0
10.0
20.0
11.0
21.0
7.0
15.0
5.0
13.0
9.0
12.0
10.0
18.0
ns
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
5
6
TOOK
TOKO
8.0
0
7.0
0
ns
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
TIOH
TIOL
FCLK
4.0
113.0
3.5
135.0
ns
MHz
Global Reset Delays (based on XC3042A)
RESET Pad to Registered In
(Q)
RESET Pad to output pad
(fast)
(slew-rate limited)
13
15
TRRI
TRPO
24.0
33.0
43.0
23.0
29.0
37.0
ns
Product Obsolete or Under Obsolescence
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