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參數(shù)資料
| 型號： | XC3195A-09PQ160C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 16/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 7500 GATE 160-PQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 484 |
| RAM 位總計： | 94984 |
| 輸入/輸出數(shù)： | 138 |
| 門數(shù)： | 7500 |
| 電源電壓： | 4.25 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 其它名稱： | Q1428091 |
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R
November 9, 1998 (Version 3.1)
7-25
XC3000 Series Field Programmable Gate Arrays
7
Configuration Timing
This section describes the configuration modes in detail.
Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the DIN input. Each
rising edge of the CCLK output increments the Serial
PROM internal address counter. This puts the next data bit
on the SPROM data output, connected to the DIN pin. The
lead FPGA accepts this data on the subsequent rising
CCLK edge.
The lead FPGA then presents the preamble data (and all
data that overflows the lead device) on its DOUT pin. There
is an internal delay of 1.5 CCLK periods, which means that
DOUT changes on the falling CCLK edge, and the next
device in the daisy-chain accepts data on the subsequent
rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
X5989_01
CE
GENERAL-
PURPOSE
USER I/O
PINS
M0
M1
PWRDWN
DOUT
M2
HDC
OTHER
I/O PINS
RESET
DIN
CCLK
DATA
CLK
+5 V
OE/RESET
XC3000
FPGA
DEVICE
D/P
SCP
CEO
CASCADED
SERIAL
MEMORY
LDC
INIT
XC17xx
RESET
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
DURING CONFIGURATION
THE 5 k
M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
BE USER I/O.
(LOW RESETS THE XC17xx ADDRESS POINTER)
TO CCLK OF OPTIONAL
VCC
VPP
+5 V
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO DIN OF OPTIONAL
IF READBACK IS
ACTIVATED, A
5-k
RESISTOR IS
REQUIRED IN
SERIES WITH M1
*
CE
DATA
CLK
OE/RESET
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
TO DIN OF OPTIONAL
INIT
+5V
Figure 23: Master Serial Mode Circuit Diagram
Product Obsolete or Under Obsolescence
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