- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1973 > XC3195A-09PQ160C (Xilinx Inc)IC FPGA 7500 GATE 160-PQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | XC3195A-09PQ160C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 18/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 7500 GATE 160-PQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 484 |
| RAM 位總計(jì)： | 94984 |
| 輸入/輸出數(shù)： | 138 |
| 門(mén)數(shù)： | 7500 |
| 電源電壓： | 4.25 V ~ 5.25 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 160-BQFP |
| 供應(yīng)商設(shè)備封裝： | 160-PQFP（28x28） |
| 其它名稱(chēng)： | Q1428091 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)當(dāng)前第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)
R
November 9, 1998 (Version 3.1)
7-27
XC3000 Series Field Programmable Gate Arrays
7
Master Parallel Mode
In Master Parallel mode, the lead FPGA directly addresses
an industry-standard byte-wide EPROM and accepts eight
data bits right before incrementing (or decrementing) the
address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data (and all data that over-
flows the lead device) on the DOUT pin. There is an inter-
nal delay of 1.5 CCLK periods, after the rising CCLK edge
that accepts a byte of data, and also changes the EPROM
address, until the falling CCLK edge that makes the LSB
(D0) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy chain accepts data on the subsequent rising
CCLK edge.
X5990
RCLK
General-
Purpose
User I/O
Pins
M0 M1PWRDWN
M2
HDC
Other
I/O Pins
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
+5 V
.....
CE
OE
FPGA
CCLK
DOUT
System Reset
A11
A12
A13
A14
A15
EPROM
RESET
...
Other
I/O Pins
DOUT
M2
HDC
LDC
FPGA
Slave #1
+5 V
M0 M1PWRDWN
CCLK
DIN
D/P
Reset
DOUT
FPGA
Slave #n
+5 V
M0 M1PWRDWN
CCLK
DIN
D/P
General-
Purpose
User I/O
Pins
RESET
Master
...
+5 V
8
INIT
...
M2
HDC
LDC
INIT
General-
Purpose
User I/O
Pins
+5 V
D/P
Other
I/O Pins
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LCA CCLK
Variations in Clear State Time.
Open
Collector
INIT
N.C.
Reprogram
5 k
5 k
5 k
5 k
Each
If Readback is
Activated, a
5-k
Resistor is
Required in
Series With M1
*
**
Figure 25: Master Parallel Mode Circuit Diagram
Product Obsolete or Under Obsolescence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3S1000L-4FGG320C | SPARTAN-3A FPGA 1M STD 320-FBGA |
| XC3S1400A-4FT256I | IC FPGA SPARTAN 3 256FTBGA |
| XC3S1400A-5FGG676C | IC SPARTAN-3A FPGA 1400K 676FBGA |
| XC3S1400AN-4FGG676I | IC FPGA SPARTAN-AN 1400K 676FBGA |
| XC3S1600E-5FGG484C | IC FPGA SPARTAN-3E 1600K 484FBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3195A-1PC84C | 制造商:Xilinx 功能描述: |
| XC3195A-1PQ160C | 制造商:Xilinx 功能描述: |
| XC3195A-1PQ208C | 制造商:Xilinx 功能描述: |
| XC3195A-2PC84C | 制造商:Xilinx 功能描述: |
| XC3195A-2PG175C | 制造商:Xilinx 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。