1. At power-up, VCC" />
參數(shù)資料
型號(hào)： XC3130A-3PQ100C
廠商： Xilinx Inc
文件頁數(shù)： 19/76頁
文件大小： 0K
描述： IC LOGIC CL ARRAY 3000GAT 100PQF
產(chǎn)品變化通告： XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
標(biāo)準(zhǔn)包裝： 66
系列： XC3000A/L
LAB/CLB數(shù)： 100
RAM 位總計(jì)： 22176
輸入/輸出數(shù)： 80
門數(shù)： 2000
電源電壓： 4.25 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 100-BQFP
供應(yīng)商設(shè)備封裝： 100-QFP（14x20）
其它名稱： 122-1041
R
XC3000 Series Field Programmable Gate Arrays
7-28
November 9, 1998 (Version 3.1)
Notes:
1. At power-up, VCC must rise from 2.0 V to VCC min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long VCC rise time of >100 ms, or a
non-monotonically rising VCC may require a >6-s High level on RESET, followed by a >6-s Low level on RESET and D/P
after VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
Figure 26: Master Parallel Mode Programming Switching Characteristics
Address for Byte n
Byte
2 TDRC
Address for Byte n + 1
D7
D6
A0-A15
(output)
D0-D7
RCLK
(output)
CCLK
(output)
DOUT
(output)
1 TRAC
7 CCLKs
CCLK
3 TRCD
Byte n - 1
X5380
Description
Symbol
Min
Max
Units
RCLK
To address valid
To data setup
To data hold
RCLK High
RCLK Low
1
2
3
TRAC
TDRC
TRCD
TRCH
TRCL
0
60
0
600
4.0
200
ns
s
Product Obsolete or Under Obsolescence
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XC3130A-3PQ100C0262 制造商:Xilinx 功能描述:
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XC3130A-3VQ64C 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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