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參數(shù)資料
| 型號： | XC3130A-3PQ100C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 14/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LOGIC CL ARRAY 3000GAT 100PQF |
| 產(chǎn)品變化通告： | XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | XC3000A/L |
| LAB/CLB數(shù)： | 100 |
| RAM 位總計： | 22176 |
| 輸入/輸出數(shù)： | 80 |
| 門數(shù)： | 2000 |
| 電源電壓： | 4.25 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 100-BQFP |
| 供應(yīng)商設(shè)備封裝： | 100-QFP（14x20） |
| 其它名稱： | 122-1041 |
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R
November 9, 1998 (Version 3.1)
7-23
XC3000 Series Field Programmable Gate Arrays
7
Special Configuration Functions
The configuration data includes control over several spe-
cial functions in addition to the normal user logic functions
and interconnect.
Input thresholds
Readback disable
DONE pull-up resistor
DONE timing
RESET timing
Oscillator frequency divided by two
Each of these functions is controlled by configuration data
bits which are selected as part of the normal development
system bitstream generation process.
Input Thresholds
Prior to the completion of configuration all FPGA input
thresholds are TTL compatible. Upon completion of config-
uration, the input thresholds become either TTL or CMOS
compatible as programmed. The use of the TTL threshold
option requires some additional supply current for thresh-
old shifting. The exception is the threshold of the
PWRDWN input and direct clocks which always have a
CMOS input. Prior to the completion of configuration the
user I/O pins each have a high impedance pull-up. The
configuration program can be used to enable the IOB
pull-up resistors in the Operational mode to act either as an
input load or to avoid a floating input on an otherwise
unused pin.
Readback
The contents of a Field Programmable Gate Array may be
read back if it has been programmed with a bitstream in
which the Readback option has been enabled. Readback
may be used for verification of configuration and as a
method of determining the state of internal logic nodes dur-
ing debugging. There are three options in generating the
configuration bitstream.
“Never” inhibits the Readback capability.
“One-time,” inhibits Readback after one Readback has
been executed to verify the configuration.
“On-command” allows unrestricted use of Readback.
Readback is accomplished without the use of any of the
user I/O pins; only M0, M1 and CCLK are used. The initia-
tion of Readback is produced by a Low to High transition of
the M0/RTRIG (Read Trigger) pin. The CCLK input must
then be driven by external logic to read back the configura-
tion data. The first three Low-to-High CCLK transitions
clock out dummy data. The subsequent Low-to-High CCLK
transitions shift the data frame information out on the
M1/RDATA (Read Data) pin. Note that the logic polarity is
always inverted, a zero in configuration becomes a one in
Readback, and vice versa. Note also that each Readback
frame has one Start bit (read back as a one) but, unlike in
configuration, each Readback frame has only one Stop bit
(read back as a zero). The third leading dummy bit men-
tioned above can be considered the Start bit of the first
frame. All data frames must be read back to complete the
process and return the Mode Select and CCLK pins to their
normal functions.
Readback data includes the current state of each CLB
flip-flop, each input flip-flop or latch, and each device pad.
These data are imbedded into unused configuration bit
positions during Readback. This state information is used
by the development system In-Circuit Verifier to provide
visibility into the internal operation of the logic while the
system is operating. To readback a uniform time-sample of
all storage elements, it may be necessary to inhibit the sys-
tem clock.
Reprogram
To initiate a re-programming cycle, the dual-function pin
DONE/PROG must be given a High-to-Low transition. To
reduce sensitivity to noise, the input signal is filtered for two
cycles of the FPGA internal timing generator. When repro-
gram begins, the user-programmable I/O output buffers are
disabled and high-impedance pull-ups are provided for the
package pins. The device returns to the Clear state and
clears the configuration memory before it indicates ‘initial-
ized’. Since this Clear operation uses chip-individual inter-
nal timing, the master might complete the Clear operation
and then start configuration before the slave has completed
the Clear operation. To avoid this problem, the slave INIT
pins must be AND-wired and used to force a RESET on the
master (see Figure 25). Reprogram control is often imple-
mented using an external open-collector driver which pulls
DONE/PROG Low. Once a stable request is recognized,
the DONE/PROG pin is held Low until the new configura-
tion has been completed. Even if the re-program request is
externally held Low beyond the configuration period, the
FPGA will begin operation upon completion of configura-
tion.
DONE Pull-up
DONE/PROG is an open-drain I/O pin that indicates the
FPGA is in the operational state. An optional internal
pull-up resistor can be enabled by the user of the develop-
ment system. The DONE/PROG pins of multiple FPGAs in
a daisy-chain may be connected together to indicate all are
DONE or to direct them all to reprogram.
DONE Timing
The timing of the DONE status signal can be controlled by
a selection to occur either a CCLK cycle before, or after, the
outputs going active. See Figure 22. This facilitates control
of external functions such as a PROM enable or holding a
system in a wait state.
Product Obsolete or Under Obsolescence
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