參數(shù)資料
型號： XC3120A-3PC68C
廠商： Xilinx Inc
文件頁數(shù)： 58/76頁
文件大?。?/td> 0K
描述： IC LOGIC CL ARRAY 2000GAT 68PLCC
產(chǎn)品變化通告： XC4000XL/E, XC9500XV, XC3100A Discontinuance 12/Apr/2010
標準包裝： 18
系列： XC3000A/L
LAB/CLB數(shù)： 64
RAM 位總計： 14779
輸入/輸出數(shù)： 58
門數(shù)： 1500
電源電壓： 4.25 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 68-LCC（J 形引線）
供應商設備封裝： 68-PLCC
其它名稱： 122-1037
R
November 9, 1998 (Version 3.1)
7-63
XC3000 Series Field Programmable Gate Arrays
7
XC3100L IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
Speed Grade
-3
-2
Description
Symbol
Min
Max
Min
Max
Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch (XC3100L)
transparent
Clock (IK) to Registered In (Q)
3
4
TPID
TPTG
TIKRI
2.2
11.0
2.2
2.0
11.0
1.9
ns
Set-up Time (Input)
Pad to Clock (IK) set-up time
XC3142L
XC3190L
1TPICK
9.5
9.9
9.0
9.4
ns
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (O) to Pad
(fast)
same
(slew-rate limited)(XC3100L)
3-state to Pad begin hi-Z
(fast)
same
(slew-rate limited)
3-state to Pad active and valid (fast)(XC3100L)
same
(slew -rate limited)
7
10
9
8
TOKPOTOK
PO
TOPF
TTSHZ
TTSON
4.4
10.0
3.3
9.0
5.5
9.0
15.0
4.0
9.7
3.0
8.7
5.0
8.5
14.2
ns
Set-up and Hold Times (Output)
Output (O) to clock (OK) set-up time (XC3100L)
Output (O) to clock (OK) hold time
5
6
TOOK
TOKO
4.0
0
3.6
0
ns
Clock
Clock High time
Clock Low time
Export Control Maximum flip-flop toggle rate
11
12
TIOH
TIOL
FTOG
1.6
270
1.3
325
ns
MHz
Global Reset Delays
RESET Pad to Registered In (Q)
(XC3142L)
(XC3190L)
RESET Pad to output pad
(fast)
(slew-rate limited)
13
15
TRRI
TRPO
16.0
21.0
17.0
23.0
16.0
21.0
17.0
23.0
ns
Advance
Product Obsolete or Under Obsolescence
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